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Travelled to:
1 × France
Collaborated with:
H.N.Nguyen J.P.Tual L.Ducousso P.Vallet
Talks about:
synthesi (1) mainfram (1) system (1) verif (1) logic (1) cach (1) cpu (1)

Person: Michel Thill

DBLP DBLP: Thill:Michel

Contributed to:

EDAC-ETC-EUROASIC 19941994

Wrote 1 papers:

EDAC-1994-NguyenTDTV #cpu #logic #synthesis #verification
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System (HNN, JPT, LD, MT, PV), pp. 60–64.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.