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Travelled to:
2 × France
Collaborated with:
H.N.Nguyen L.Ducousso M.Thill P.Vallet M.Renaudin G.F.Bouesse P.Proust L.Sourgen F.Germain
Talks about:
smartcard (1) synthesi (1) mainfram (1) system (1) verif (1) secur (1) logic (1) high (1) cach (1) cpu (1)

Person: J. P. Tual

DBLP DBLP: Tual:J=_P=

Contributed to:

DATE v1 20042004
EDAC-ETC-EUROASIC 19941994

Wrote 2 papers:

DATE-v1-2004-RenaudinBPTSG #security
High Security Smartcards (MR, GFB, PP, JPT, LS, FG), pp. 228–233.
EDAC-1994-NguyenTDTV #cpu #logic #synthesis #verification
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System (HNN, JPT, LD, MT, PV), pp. 60–64.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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