70 papers:
DAC-2015-HanF #analysis #approach #cpu #gpu #graph #scalability- Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems (LH, ZF), p. 6.
- DAC-2015-KadjoAKG #approach #cpu #energy #gpu #mobile #performance
- A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms (DK, RA, MK, PVG), p. 6.
DATE-2015-BruggerVWTK #cpu #hybrid- Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems (CB, JAV, NW, ST, RK), pp. 1599–1602.
SIGIR-2015-CatenaMT #cpu #power management #web- Load-sensitive CPU Power Management for Web Search Engines (MC, CM, NT), pp. 751–754.
SAC-2015-JoCKBO #algorithm #approach #collaboration #cpu #data-driven #on the- On running data-intensive algorithms with intelligent SSD and host CPU: a collaborative approach (YYJ, SC, SWK, DHB, HO), pp. 2060–2065.
ICSE-v2-2015-Salgado #behaviour #cpu #gpu #interactive #kernel #profiling- Profiling Kernels Behavior to Improve CPU / GPU Interactions (RS), pp. 754–756.
CGO-2015-KimHSLH #architecture #concurrent #cpu #modelling #programming #scheduling #thread- Locality-centric thread scheduling for bulk-synchronous programming models on CPU architectures (HSK, IEH, JAS, SSL, WmWH), pp. 257–268.
HPCA-2015-AroraMPJT #behaviour #benchmark #comprehension #cpu #gpu #metric #power management- Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (MA, SM, IP, NJ, DMT), pp. 366–377.
HPDC-2015-XiaoCHZ #cpu #gpu #monte carlo- Monte Carlo Based Ray Tracing in CPU-GPU Heterogeneous Systems and Applications in Radiation Therapy (KX, DZC, XSH, BZ), pp. 247–258.
PPoPP-2015-PiaoKOLKKL #adaptation #cpu #framework #gpu #javascript #named- JAWS: a JavaScript framework for adaptive CPU-GPU work sharing (XP, CK, YO, HL, JK, HK, JWL), pp. 251–252.
SOSP-2015-AmitTSAS #cpu #validation- Virtual CPU validation (NA, DT, AS, AA, ES), pp. 311–327.
- DAC-2014-KoKYKH #cpu #gpu #simulation
- Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms (YK, TK, YY, MK, SH), p. 6.
- DAC-2014-NandakumarM #analysis
- System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs (VSN, MMS), p. 6.
- DAC-2014-PathaniaJPM #3d #cpu #game studies #gpu #mobile #power management
- Integrated CPU-GPU Power Management for 3D Mobile Games (AP, QJ, AP, TM), p. 6.
VLDB-2015-HeZH14 #architecture #cpu #gpu #query- In-Cache Query Co-Processing on Coupled CPU-GPU Architectures (JH, SZ, BH), pp. 329–340.
ICPR-2014-GarciaO #realtime- CPU-Based Real-Time Surface and Solid Voxelization for Incomplete Point Cloud (FG, BEO), pp. 2757–2762.
ASPLOS-2014-PichaiHB #architecture #cpu #design #memory management- Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces (BP, LH, AB), pp. 743–758.
ISSTA-2014-NejatiB #constraints #cpu #identification #trade-off #using- Identifying optimal trade-offs between CPU time usage and temporal constraints using search (SN, LCB), pp. 351–361.
ASE-2013-NejatiABHBC #cpu #embedded #risk management- Minimizing CPU time shortage risks in integrated embedded software (SN, MA, LCB, JH, JB, YC), pp. 529–539.
- DATE-2013-ZakharenkoAM #cpu #gpu #performance #using
- Characterizing the performance benefits of fused CPU/GPU systems using FusionSim (VZ, TMA, AM), pp. 685–688.
- VLDB-2013-HeLH #architecture #cpu #gpu
- Revisiting Co-Processing for Hash Joins on the Coupled CPU-GPU Architecture (JH, ML, BH), pp. 889–900.
- VLDB-2013-ZhangHHL #architecture #cpu #gpu #named #parallel #performance #query #towards
- OmniDB: Towards Portable and Efficient Query Processing on Parallel CPU/GPU Architectures (SZ, JH, BH, ML), pp. 1374–1377.
- VLDB-2014-DasNLS13 #as a service #cpu #multitenancy #performance #relational
- CPU Sharing Techniques for Performance Isolation in Multitenant Relational Database-as-a-Service (SD, VRN, FL, MS), pp. 37–48.
- HPCA-2013-LustigM #cpu #fine-grained #gpu #latency
- Reducing GPU offload latency via fine-grained CPU-GPU synchronization (DL, MM), pp. 354–365.
- PPoPP-2013-YangXFGLXLSYZ #algorithm #cpu #gpu #simulation
- A peta-scalable CPU-GPU algorithm for global atmospheric simulations (CY, WX, HF, LG, LL, YX, YL, JS, GY, WZ), pp. 1–12.
- DAC-2012-JeongESP #cpu #gpu #memory management
- A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC (MKJ, ME, CS, NCP), pp. 850–855.
- DAC-2012-KimLCKWYL #cpu #gpu #hybrid #in memory #memory management
- Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU (DK, SL, JC, DK, DHW, SY, SL), pp. 888–896.
- VLDB-2012-WangHLWZS #cpu #gpu #hybrid #image
- Accelerating Pathology Image Data Cross-Comparison on CPU-GPU Hybrid Systems (KW, YH, RL, FW, XZ, JHS), pp. 1543–1554.
ITiCSE-2012-Black #cpu #design #education #hardware- A hardware simulator for teaching CPU design (MB), p. 380.
MoDELS-2012-NejatiASB #analysis #cpu #embedded #modelling #safety #testing- Modeling and Analysis of CPU Usage in Safety-Critical Embedded Systems to Support Stress Testing (SN, SDA, MS, LCB), pp. 759–775.
- MoDELS-2012-NejatiASB #analysis #cpu #embedded #modelling #safety #testing
- Modeling and Analysis of CPU Usage in Safety-Critical Embedded Systems to Support Stress Testing (SN, SDA, MS, LCB), pp. 759–775.
- CGO-2012-JablinJPLA #architecture #cpu #gpu
- Dynamically managed data for CPU-GPU architectures (TBJ, JAJ, PP, FL, DIA), pp. 165–174.
- HPCA-2012-AyoubNR #cpu #energy #memory management #named
- JETC: Joint energy thermal and cooling management for memory and CPU subsystems in servers (RZA, RN, TR), pp. 299–310.
- HPCA-2012-LeeK #architecture #cpu #gpu #named #policy
- TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture (JL, HK), pp. 91–102.
- HPCA-2012-YangXMZ #architecture #cpu #gpu
- CPU-assisted GPGPU on fused CPU-GPU architectures (YY, PX, MM, HZ), pp. 103–114.
- HPDC-2012-XuGRKKX #cpu #named #scheduling #slicing #virtual machine
- vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing (CX, SG, PNR, AK, RRK, DX), pp. 3–14.
OSDI-2012-BelayBMTMK #cpu #named- Dune: Safe User-level Access to Privileged CPU Features (AB, AB, AJM, DT, DM, CK), pp. 335–348.
- PPoPP-2012-KimSLNJL #clustering #cpu #gpu #programming
- OpenCL as a unified programming model for heterogeneous CPU/GPU clusters (JK, SS, JL, JN, GJ, JL), pp. 299–300.
- DAC-2011-ZhuDC #architecture #cpu #gpu #named
- Hermes: an integrated CPU/GPU microarchitecture for IP routing (YZ, YD, YC), pp. 1044–1049.
PLDI-2011-JablinPJJBA #automation #communication #cpu #gpu #optimisation- Automatic CPU-GPU communication management and optimization (TBJ, PP, JAJ, NPJ, SRB, DIA), pp. 142–151.
- HPDC-2011-LiLTCZ #3d #cpu #experience #gpu #re-engineering
- Experience of parallelizing cryo-EM 3D reconstruction on a CPU-GPU heterogeneous system (LL, XL, GT, MC, PZ), pp. 195–204.
- DATE-2010-ZhuSJ #configuration management #cpu #design #performance #streaming
- Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (JZ, IS, AJ), pp. 1035–1040.
- HPCA-2010-TangBHC #architecture #cpu #performance #using
- DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance (DT, YB, WH, MC), pp. 1–12.
- PPoPP-2010-PerarnauH #cpu #generative #named
- KRASH: reproducible CPU load generation on many cores machines (SP, GH), pp. 327–328.
- DATE-2009-ZhuSJ #architecture #cpu #hybrid #realtime #scheduling #streaming
- Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (JZ, IS, AJ), pp. 1506–1511.
- ISSTA-2009-MartignoniPRB #cpu #testing
- Testing CPU emulators (LM, RP, GFR, DB), pp. 261–272.
- VLDB-2008-ChhuganiNLMHCBKD #architecture #cpu #implementation #manycore #performance #sorting
- Efficient implementation of sorting on multi-core SIMD CPU architecture (JC, ADN, VWL, WM, MH, YKC, AB, SK, PD), pp. 1313–1324.
- SAC-2008-SchobelP #case study #clustering #cpu #kernel #research #scheduling #using
- Kernel-mode scheduling server for CPU partitioning: a case study using the Windows research kernel (MS, AP), pp. 1700–1704.
- HPCA-2008-DiaoS #cpu #predict #process
- Prediction of CPU idle-busy activity pattern (QD, JJS), pp. 27–36.
LCTES-2007-AbouGhazalehFRXLCMM #cpu #machine learning #scalability #using- Integrated CPU and l2 cache voltage scaling using machine learning (NA, APF, CR, RX, FL, BRC, DM, RGM), pp. 41–50.
- PPoPP-2007-KejariwalTGLKBNVP #analysis #concurrent #cpu #performance #specification #thread #using
- Tight analysis of the performance potential of thread speculation using spec CPU 2006 (AK, XT, MG, WL, SK, UB, AN, AVV, CDP), pp. 215–225.
QAPL-2005-BinderH06 #bytecode #cpu #metric #using- Using Bytecode Instruction Counting as Portable CPU Consumption Metric (WB, JH), pp. 57–77.
PEPM-2004-HulaasB #cpu #java #program transformation- Program transformations for portable CPU accounting and control in Java (JH, WB), pp. 169–177.
- HPDC-2004-AndradeBCM #grid #peer-to-peer
- Discouraging Free Riding in a Peer-to-Peer CPU-Sharing Grid (NA, FVB, WC, MM), pp. 129–137.
- PLDI-2003-HsuK #algorithm #compilation #cpu #design #energy #evaluation #implementation #reduction
- The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction (CHH, UK), pp. 38–48.
- SOSP-2003-YuanN #cpu #energy #mobile #multi #realtime #scheduling
- Energy-efficient soft real-time CPU scheduling for mobile multimedia systems (WY, KN), pp. 149–163.
- DAC-2002-RichardsonHHZSL #cpu
- The iCOREtm 520 MHz synthesizable CPU core (NR, LBH, RH, TZ, NS, JL), pp. 640–645.
- DATE-2001-TagoHINSY #cpu
- CPU for PlayStation 2 (HT, KH, NI, MN, MS, YY), p. 696.
- VLDB-2000-ManegoldBK #cpu #memory management #optimisation #what
- What Happens During a Join? Dissecting CPU and Memory Optimization Effects (SM, PAB, MLK), pp. 339–350.
- OSDI-2000-ChandraAGS #algorithm #cpu #multi #scheduling #symmetry
- Surplus Fair Scheduling: A Proportional-Share CPU Scheduling Algorithm for Symmetric Multiprocessors (AC, MA, PG, PJS), pp. 45–58.
- HPDC-1999-WolskiSH #cpu #grid #predict
- Predicting the CPU Availability of Time-shared Unix Systems on the Computational Grid (RW, NTS, JH), pp. 105–112.
- DAC-1997-ShacklefordYOKTY #design #embedded #optimisation
- Memory-CPU Size Optimization for Embedded System Designs (BS, MY, EO, HK, HT, HY), pp. 246–251.
- SOSP-1997-JonesRR #constraints #cpu #independence #performance #predict #process #scheduling
- CPU Reservations and Time Constraints: Efficient, Predictable Scheduling of Independent Activities (MBJ, DR, MCR), pp. 198–211.
- DAC-1996-DesaiCJ #cpu #network #performance
- Sizing of Clock Distribution Networks for High Performance CPU Chips (MPD, RC, JJ), pp. 389–394.
- DAC-1996-DesaiY #cpu #design #simulation #using #verification
- A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation (MPD, YTY), pp. 125–130.
- HPDC-1996-NurmiBGLP #automation #cpu #distributed #network
- Automatic Management of CPU and I/O Bottlenecks in Distributed Applications on ATM Networks (MAN, WEB, RNG, KCL, MDP), pp. 481–489.
- EDAC-1994-NguyenTDTV #cpu #logic #synthesis #verification
- Logic Synthesis and Verification of the CPU and Caches of a Mainframe System (HNN, JPT, LD, MT, PV), pp. 60–64.
TRI-Ada-1994-GreeneL #cpu #embedded #migration- Embedded CPU Target Migration, Doing More With Less (RG, GL), pp. 429–436.
SIGMOD-1987-GrayP #cpu #memory management- The 5 Minute Rule for Trading Memory for Disk Accesses and The 10 Byte Rule for Trading Memory for CPU Time (JG, GRP), pp. 395–398.
- DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random
- Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
