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Travelled to:
1 × USA
Collaborated with:
W.Liu T.Wang
Talks about:
floorplan (1) interpos (1) silicon (1) signal (1) assign (1) base (1)

Person: Min-Sheng Chang

DBLP DBLP: Chang:Min=Sheng

Contributed to:

DAC 20142014

Wrote 1 papers:

DAC-2014-LiuCW #3d
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs (WHL, MSC, TCW), p. 6.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.