Stem floorplan$ (all stems)

59 papers:

DATE-2015-LourencoMH #using

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.

DATE-2015-PaganoVRCSS #configuration management

Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems (DP, MV, MR, RC, DS, MDS), pp. 920–923.

DAC-2014-LiuCW #3d

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs (WHL, MSC, TCW), p. 6.

DAC-2014-NandakumarM #analysis

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs (VSN, MMS), p. 6.

DATE-2013-UnutulmazDF #optimisation #using

Area optimization on fixed analog floorplans using convex area functions (AU, GD, FVF), pp. 1843–1848.

DAC-2011-KungHSS #optimisation

Thermal signature: a simple yet accurate thermal index for floorplan optimization (JK, IH, SSS, YS), pp. 108–113.

DATE-2011-XueJZZ #evaluation #performance

Floorplanning exploration and performance evaluation of a new Network-on-Chip (LX, WJ, QZ, YZ), pp. 625–630.

ICDAR-2011-HerasMSV #architecture #segmentation

Wall Patch-Based Segmentation in Architectural Floorplans (LPdlH, JM, GS, EV), pp. 1270–1274.

DATE-2010-GhoshS #performance #perspective

Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PG, AS), pp. 654–657.

DATE-2010-LiSC #logic #manycore

Exploiting local logic structures to optimize multi-core SoC floorplanning (CHL, SS, LPC), pp. 1291–1296.

DAC-2008-SenguptaS #design

Application-driven floorplan-aware voltage island design (DS, RAS), pp. 155–160.

DATE-2007-MogalB #architecture #reduction

Microarchitecture floorplanning for sub-threshold leakage reduction (HM, KB), pp. 1238–1243.

DAC-2006-MoffittNMP #constraints

Constraint-driven floorplan repair (MDM, ANN, ILM, MEP), pp. 1103–1108.

DAC-2006-ShamYC

Optimal cell flipping in placement and floorplanning (CWS, EFYY, CCNC), pp. 1109–1114.

DATE-2006-HealyVEBLLL #architecture #performance #trade-off

Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.

DATE-2006-WongL #3d

3D floorplanning with thermal vias (EW, SKL), pp. 878–883.

DAC-2005-NookalaCLS #approach #architecture #design #statistics #using

Microarchitecture-aware floorplanning using a statistical design of experiments approach (VN, YC, DJL, SSS), pp. 579–584.

DAC-2005-PasrichaDBB #architecture #automation #communication #synthesis

Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.

DAC-2004-EkpanyapongMWLL #architecture #design

Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.

DAC-2004-LongSLH #optimisation #pipes and filters

Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects (CL, LJS, WL, LH), pp. 640–645.

DATE-DF-2004-Auletta

Expert System Perimeter Block Placement Floorplanning (RA), pp. 140–143.

DATE-v1-2004-BrandtnerW #named #simulation

SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level (TB, RW), pp. 616–621.

DATE-v2-2004-HsiehH #design #effectiveness

A New Effective Congestion Model in Floorplan Design (YLH, TMH), pp. 1204–1209.

DAC-2003-LeeCHY #multi #scalability #using

Multilevel floorplanning/placement for large-scale modules using B*-trees (HCL, YWC, JMH, HHY), pp. 812–817.

DATE-2003-LaiYC #evaluation #performance

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees (STWL, EFYY, CCNC), pp. 10856–10861.

DAC-2002-LinC #named #orthogonal

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans (JML, YWC), pp. 842–847.

DAC-2002-TangW #constraints #performance

Floorplanning with alignment and performance constraints (XT, DFW), pp. 848–853.

DATE-2002-ChuY #design

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design (CCNC, EFYY), p. 1101.

DATE-2002-LeeLFCH #problem

A New Formulation for SOC Floorplan Area Minimization Problem (CHL, YCL, WYF, CCC, TMH), p. 1100.

DATE-2002-WongSY #design #estimation

Congestion Estimation with Buffer Planning in Floorplan Design (WCW, CWS, EFYY), pp. 696–701.

DAC-2001-LinC #graph #named #representation #transitive

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans (JML, YWC), pp. 764–769.

DAC-2001-MaHDCCG #constraints

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List (YM, XH, SD, YC, CKC, JG), pp. 770–775.

DATE-2001-LaiW #representation #slicing

Slicing tree is a complete floorplan representation (ML, DFW), pp. 228–232.

DAC-2000-ChangCWW #representation

B*-Trees: a new representation for non-slicing floorplans (YCC, YWC, GMW, SWW), pp. 458–463.

DAC-2000-ChenK #approximate #linear #programming

Floorplan sizing by linear programming approximation (PC, ESK), pp. 468–471.

DAC-1999-GuoCY #representation

An O-Tree Representation of Non-Slicing Floorplan and Its Applications (PNG, CKC, TY), pp. 268–273.

DAC-1999-SuWL #interactive

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (HPS, ACHW, YLL), pp. 262–267.

DAC-1999-YimBK

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.

DAC-1998-EisenmannJ

Generic Global Placement and Floorplanning (HE, FMJ), pp. 269–274.

DAC-1998-SalekLP #design

A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together (AHS, JL, MP), pp. 128–134.

STOC-1997-He #graph #on the

On Floorplans of Planar Graphs (XH), pp. 426–435.

DAC-1996-ChenH #algorithm #approximate #performance

Efficient Approximation Algorithms for Floorplan Area Minimization (DZC, XH), pp. 483–486.

DAC-1993-Lee #2d #algorithm #bound #design

A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules (TcL), pp. 525–530.

DAC-1992-Sur-KolayB #canonical

Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning (SSK, BBB), pp. 69–74.

DAC-1992-WangW #graph #optimisation

A Graph Theoretic Technique to Speed up Floorplan Area Optimization (TCW, DFW), pp. 62–68.

DAC-1991-WengP #3d #scheduling #synthesis

3D Scheduling: High-Level Synthesis with Floorplanning (JPW, ACP), pp. 668–673.

DAC-1990-BrasenB #algorithm #named #optimisation

MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing (DRB, MLB), pp. 107–110.

DAC-1990-SutanthavibulSR #approach #design #optimisation

An Analytical Approach to Floorplan Design and Optimization (SS, ES, JBR), pp. 187–192.

DAC-1990-WangW #algorithm #optimisation

An Optimal Algorithm for Floorplan Area Optimization (TCW, DFW), pp. 180–186.

DAC-1989-GabbeS #clustering

A Note on Clustering Modules for Floorplanning (JDG, PAS), pp. 594–597.

DAC-1989-JabriS #algorithm #knowledge-based #named #top-down

PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System (MAJ, DJS), pp. 582–585.

DAC-1989-PrasitjutrakulK #approach #programming

Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement (SP, WJK), pp. 364–369.

DAC-1989-SastryP #clustering #problem #statistics

An Investigation into Statistical Properties of Partitioning and Floorplanning Problems (SS, JIP), pp. 382–387.

DAC-1989-WongS #optimisation #performance

Efficient Floorplan Area Optimization (DFW, PSS), pp. 586–589.

DAC-1987-KoukaS #data analysis #design

An Application of Exploratory Data Analysis Techniques to Floorplan Design (EFMK, GS), pp. 654–658.

DAC-1986-WatanabeA #design #named

Flute — a floorplanning agent for full custom VLSI design (HW, BDA), pp. 601–607.

DAC-1986-WongL #algorithm #design

A new algorithm for floorplan design (DFW, CLL), pp. 101–107.

DAC-1983-Leblond #named

CAF: A computer-assisted floorplanning tool (AL), pp. 747–753.

DAC-1982-Otten #automation #design

Automatic floorplan design (RHJMO), pp. 261–267.