Travelled to:1 × Germany
4 × USA
Collaborated with:D.F.Wong W.Liu T.Hsu M.Chang T.Chien S.Popovych H.Lai C.Wang Y.Li H.Chien Z.Peng Y.Wu T.Wang H.Lin C.Wu
Talks about:floorplan (3) optim (3) awar (3) algorithm (2) interpos (2) silicon (2) cost (2) base (2) area (2) manufactur (1)
Person: Ting-Chi Wang
DBLP: Wang:Ting=Chi
Contributed to:
2014
2014200819921990Wrote 7 papers:
- DAC-2014-LiuCW #3d
- Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs (WHL, MSC, TCW), p. 6.
- DAC-2014-PopovychLWLLW
- Density-aware Detailed Placement with Instant Legalization (SP, HHL, CMW, YLL, WHL, TCW), p. 6.
- DATE-2014-ChienPWWLWW #cost analysis
- Mask-cost-aware ECO routing∗ (HAC, ZYP, YRW, THW, HCL, CFW, TCW), pp. 1–4.
- DATE-2014-LiuCW
- Metal layer planning for silicon interposers with consideration of routability and manufacturing cost (WHL, TKC, TCW), pp. 1–6.
- DAC-2008-HsuW #algorithm #memory management #network #power management
- A generalized network flow based algorithm for power-aware FPGA memory mapping (TYH, TCW), pp. 30–33.
- DAC-1992-WangW #graph #optimisation
- A Graph Theoretic Technique to Speed up Floorplan Area Optimization (TCW, DFW), pp. 62–68.
- DAC-1990-WangW #algorithm #optimisation
- An Optimal Algorithm for Floorplan Area Optimization (TCW, DFW), pp. 180–186.