1 × Germany
3 × USA
Y.Li T.Wang M.Chang T.Chien C.Koh W.Kao K.Chao S.Popovych H.Lai C.Wang Y.Wei C.C.N.Sze C.J.Alpert Z.Li N.Viswanathan
rout (3) placement (2) interpos (2) silicon (2) routabl (2) awar (2) manufactur (1) constraint (1) floorplan (1) consider (1)
Person: Wen-Hao Liu
Wrote 6 papers:
- DAC-2014-LiuCW #3d
- Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs (WHL, MSC, TCW), p. 6.
- Density-aware Detailed Placement with Instant Legalization (SP, HHL, CMW, YLL, WHL, TCW), p. 6.
- Metal layer planning for silicon interposers with consideration of routability and manufacturing cost (WHL, TKC, TCW), pp. 1–6.
- DAC-2013-LiuKL #optimisation
- Optimization of placement solutions for routability (WHL, CKK, YLL), p. 9.
- DAC-2013-LiuWSALLV #constraints #design #estimation
- Routing congestion estimation with real design constraints (WHL, YW, CCNS, CJA, ZL, YLL, NV), p. 8.
- DAC-2010-LiuKLC #bound #concurrent #multi #thread
- Multi-threaded collision-aware global routing with bounded-length maze routing (WHL, WCK, YLL, KYC), pp. 200–205.