Stem silicon$ (all stems)

159 papers:

DAC-2015-GnadSKRSH #named #variability

Hayat: harnessing dark silicon and variability for aging deceleration and balancing (DG, MS, FK, SR, DS, JH), p. 6.

DAC-2015-GuoDJFM #formal method #perspective #security #validation #verification

Pre-silicon security verification and validation: a formal perspective (XG, RGD, YJ, FF, PM), p. 6.

DAC-2015-HenkelKPS #roadmap

New trends in dark silicon (JH, HK, SP, MS), p. 6.

DAC-2015-KhdrPSH #resource management

Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.

DAC-2015-RayYBB #correctness #design #security #validation

Correctness and security at odds: post-silicon validation of modern SoC designs (SR, JY, AB, SB), p. 6.

DAC-2015-ZaheerWGL #markov #named #performance #process

mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process (MZ, FW, CG, XL), p. 6.

DAC-2015-ZhanOGZ0 #approach #named #network #power management #towards

DimNoC: a dim silicon approach towards power-efficient on-chip network (JZ, JO, FG, JZ, YX), p. 6.

DATE-2015-BokhariJSHP #adaptation

Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.

DATE-2015-ChenWLL #debugging

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC (HCC, CRW, KSML, KJL), pp. 1281–1284.

DATE-2015-HaghbayanRFLPNT #manycore #online #power management #testing

Power-aware online testing of manycore systems in the dark silicon era (MHH, AMR, MF, PL, JP, ZN, HT), pp. 435–440.

DATE-2015-KapadiaP #adaptation #named #parallel #scheduling

VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era (NAK, SP), pp. 1060–1065.

DATE-2015-KhanSH #adaptation #manycore #power management

Power-efficient accelerator allocation in adaptive dark silicon many-core systems (MUKK, MS, JH), pp. 916–919.

DATE-2015-LinSKRM #debugging #detection #effectiveness #fault #performance #testing #validation

Quick error detection tests with fast runtimes for effective post-silicon validation and debug (DL, ES, SK, ER, SM), pp. 1168–1173.

DATE-2015-MohammadiGM #fault #modelling

Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.

DATE-2015-ReichPEB #component #design #flexibility #proving

Silicon proof of the intelligent analog IP design flow for flexible automotive components (TR, HDBP, UE, RB), pp. 403–404.

DATE-2015-ShafiqueGGH #manycore #variability

Variability-aware dark silicon management in on-chip many-core systems (MS, DG, SG, JH), pp. 387–392.

DATE-2015-TaatizadehN #automation #design #detection #embedded #validation

A methodology for automated design of embedded bit-flips detectors in post-silicon validation (PT, NN), pp. 73–78.

DAC-2014-BokhariJSHP #design #energy #multi #named

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.

DAC-2014-KriebelRSSH #adaptation #fault #named

ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era (FK, SR, DS, MS, JH), p. 6.

DAC-2014-LiuCW #3d

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs (WHL, MSC, TCW), p. 6.

DAC-2014-MukherjeeL

Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits (PM, PL), p. 6.

DAC-2014-NahirDKRRSSW #validation

Post-Silicon Validation of the IBM POWER8 Processor (AN, MD, SK, KR, WR, KDS, KS, GW), p. 6.

DAC-2014-ShafiqueGHM #challenge #reliability #variability

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives (MS, SG, JH, DM), p. 6.

DAC-2014-SutariaRZRMC #modelling #random #simulation #validation

BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation (KS, AR, RZ, RR, YM, YC), p. 6.

DAC-2014-ZhanXS #fine-grained #named

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era (JZ, YX, GS), p. 6.

DATE-2014-BhuniaRHRYMF #logic #towards

Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic (SB, VR, TH, SR, RY, MM, PXLF), pp. 1–6.

DATE-2014-CongLYX #evaluation #prototype #testing #validation

Coverage evaluation of post-silicon validation tests with virtual prototypes (KC, LL, ZY, FX), pp. 1–6.

DATE-2014-FourmigueBN #3d #performance #simulation

Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias (AF, GB, GN), pp. 1–6.

DATE-2014-FriedlerKMNS #effectiveness #locality #slicing #using

Effective post-silicon failure localization using dynamic program slicing (OF, WK, AM, AN, VS), pp. 1–6.

DATE-2014-LiuCW

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost (WHL, TKC, TCW), pp. 1–6.

DATE-2014-SabrySARM #generative

Integrated microfluidic power generation and cooling for bright silicon MPSoCs (MMS, AS, DA, PR, BM), pp. 1–6.

DATE-2014-SilvanoPXS #architecture #manycore

Voltage island management in near threshold manycore architectures to mitigate dark silicon (CS, GP, SX, ISS), pp. 1–6.

DATE-2014-Taylor #design

A landscape of the new dark silicon design regime (MBT), p. 1.

DATE-2014-WeberTGHKM #challenge #configuration management

Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges (WMW, JT, MG, AH, MK, TM), pp. 1–6.

DATE-2014-ZhangAJC #manycore #network

Thermal management of manycore systems with silicon-photonic networks (TZ, JLA, AJ, AKC), pp. 1–6.

DATE-2014-ZhangLHCW #multi #performance #predict

Joint Virtual Probe: Joint exploration of multiple test items’ spatial patterns for efficient silicon characterization and test prediction (SZ, FL, CKH, KTC, HW), pp. 1–6.

DAC-2013-LeiXC #consistency #prototype

Post-silicon conformance checking with virtual prototypes (LL, FX, KC), p. 6.

DAC-2013-MuthukaruppanPVMV #manycore #power management #symmetry

Hierarchical power management for asymmetric multi-core in dark silicon era (TSM, MP, VV, TM, SV), p. 9.

DAC-2013-ZhangPFH

Lighting the dark silicon by exploiting heterogeneity on future processors (YZ, LP, XF, YH), p. 7.

DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.

DATE-2013-ChandranSP #validation

Space sensitive cache dumping for post-silicon validation (SC, SRS, PRP), pp. 497–502.

DATE-2013-DeOrioLBB #debugging #detection #machine learning

Machine learning-based anomaly detection for post-silicon bug diagnosis (AD, QL, MB, VB), pp. 491–496.

DATE-2013-LiD #approach #debugging #hybrid #performance

A hybrid approach for fast and accurate trace signal selection for post-silicon debug (ML, AD), pp. 485–490.

DATE-2013-LinHLFGHM #challenge #detection #fault #validation

Overcoming post-silicon validation challenges through quick error detection (QED) (DL, TH, YL, FF, DSG, NH, SM), pp. 320–325.

DATE-2013-PaternaR #problem #using

Mitigating dark-silicon problems using superlattice-based thermoelectric coolers (FP, SR), pp. 1391–1394.

DATE-2013-RaghunathanTGM #multi #named #process

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.

DATE-2013-ZhangYH0 #testing

Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.

DAC-2012-BobbaMLM #physics #synthesis

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.

DAC-2012-ForteS #on the #proximity

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction (DF, AS), pp. 96–105.

DAC-2012-KarakonstantisRBB #fault #on the

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon (GK, CR, CB, AB), pp. 510–515.

DAC-2012-LinHFHM #debugging #detection #effectiveness #validation

Quick detection of difficult bugs for effective post-silicon validation (DL, TH, FF, NH, SM), pp. 561–566.

DAC-2012-Taylor

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse (MBT), pp. 1131–1136.

DAC-2012-WangKPRLFMP #adaptation #design #optimisation #statistics

Statistical design and optimization for adaptive post-silicon tuning of MEMS filters (FW, GK, AP, JR, XL, GKF, TM, LTP), pp. 176–181.

DAC-2012-YuanLX #configuration management #debugging #named

X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug (FY, XL, QX), pp. 555–560.

DAC-2012-ZhaoSL #3d #analysis

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs (XZ, MS, SKL), pp. 157–162.

DATE-2012-LiDX #process

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations (ML, AD, LX), pp. 1591–1596.

HPCA-2012-YanLHLGL #architecture #hybrid #manycore #named #performance

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture (GY, YL, YH, XL, MG, XL), pp. 287–298.

CAV-2012-PaulaHN #debugging #named #nondeterminism

nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces (FMdP, AJH, AN), pp. 513–531.

CASE-2011-PurwinsNBHKLPW #predict

Regression methods for prediction of PECVD Silicon Nitride layer thickness (HP, AN, BB, UH, AK, BL, GP, KW), pp. 387–392.

CASE-2011-SustoBL #maintenance #predict

A Predictive Maintenance System for Silicon Epitaxial Deposition (GAS, AB, CDL), pp. 262–267.

DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread

Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.

DAC-2011-AdirNSZMS #validation #verification

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.

DAC-2011-CongLS #3d

Thermal-aware cell and through-silicon-via co-placement for 3D ICs (JC, GL, YS), pp. 670–675.

DAC-2011-MillerBHDCB #analysis #testing #validation

A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation (GM, BB, YCH, JD, XC, GB), pp. 575–578.

DAC-2011-NowrozWR #modelling #using

Improved post-silicon power modeling using AC lock-in techniques (ANN, GW, SR), pp. 101–106.

DAC-2011-SingermanAB #transaction #validation

Transaction based pre-to-post silicon validation (ES, YA, SB), pp. 564–568.

DATE-2011-AdirCLNSZMS #validation #verification

A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.

DATE-2011-AitkenYF #correlation #modelling #parametricity

Correlating models and silicon for improved parametric yield (RA, GY, DF), pp. 1159–1163.

DATE-2011-EnemanCMMCMMBHP #estimation #multi

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (GE, JC, VM, DM, MC, KDM, AM, EB, TH, GVdP), pp. 505–506.

DATE-2011-LandrockOCKA #2d #3d #integration

2D and 3D integration with organic and silicon electronics (CKL, BO, YC, BK, JA), pp. 899–904.

DATE-2011-LiuX #debugging #multi #on the

On multiplexed signal tracing for post-silicon debug (XL, QX), pp. 685–690.

DATE-2011-WangNKWRLMB #configuration management #using

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches (XW, SN, ARK, FGW, SR, THL, MM, SB), pp. 1065–1070.

DATE-2011-XuPM

Analytical heat transfer model for thermal through-silicon vias (HX, VFP, GDM), pp. 395–400.

DHM-2011-LiT #3d

In Silicon Study of 3D Elbow Kinematics (KL, VT), pp. 139–142.

CASE-2010-AshrafTANBT #analysis #array

Structural and microfluidic analysis of MEMS based out-of-plane hollow silicon microneedle array for drug delivery (MWA, ST, NA, AN, ELB, AT), pp. 258–262.

DAC-2010-CallegariDWA #classification #learning #using

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch (NC, DGD, LCW, MSA), pp. 374–379.

DAC-2010-ConstantinidesA #debugging #testing #using

Using introspective software-based testing for post-silicon debug and repair (KC, TMA), pp. 537–542.

DAC-2010-GoodenoughA #design

Post-silicon is too late avoiding the $50 million paperweight starts with validated designs (JG, RA), pp. 8–11.

DAC-2010-KeshavaHP #challenge #how #validation

Post-silicon validation challenges: how EDA and academia can help (JK, NH, CP), pp. 3–7.

DAC-2010-MitraSN #challenge #validation

Post-silicon validation opportunities, challenges and recent advances (SM, SAS, NN), pp. 12–17.

DAC-2010-NahirZGHACBFBK #validation #verification

Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.

DAC-2010-ParkBWM #debugging #graph #locality #named #using

BLoG: post-silicon bug localization in processors using bug localization graphs (SBP, AB, HW, SM), pp. 368–373.

DAC-2010-XieD #predict #variability

Representative path selection for post-silicon timing prediction under variability (LX, AD), pp. 386–391.

DAC-2010-XieDS

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations (LX, AD, KKS), pp. 274–279.

DATE-2010-AlpaslanDKMHW #simulation

NIM- a noise index model to estimate delay discrepancies between silicon and simulation (EA, JD, BK, AKM, WMH, PvdW), pp. 1373–1376.

DATE-2010-KlumppRW #3d

3D-integration of silicon devices: A key technology for sophisticated products (AK, PR, RW), pp. 1678–1683.

DATE-2010-NeishaburiZ #clustering #debugging #performance

Enabling efficient post-silicon debug by clustering of hardware-assertions (MHN, ZZ), pp. 985–988.

DATE-2010-WeerasekeraGPT #3d #on the

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.

DAC-2009-DingZHCP #framework #integration #named #power management

O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.

DAC-2009-FickDHBBS #named #network #reliability

Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.

DAC-2009-LiuX #design #validation

Interconnection fabric design for tracing signals in post-silicon validation (XL, QX), pp. 352–357.

DATE-2009-AraniHPCYPTC #3d #reliability

Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.

DATE-2009-LiuX #validation

Trace signal selection for visibility enhancement in post-silicon validation (XL, QX), pp. 1338–1343.

DATE-2009-NagarajK #case study #process

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (KN, SK), pp. 292–295.

DATE-2009-PaciBB #adaptation #bias #communication #effectiveness #variability

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (GP, DB, LB), pp. 1404–1409.

DATE-2009-YangNV #automation #data analysis #debugging

Automated data analysis solutions to silicon debug (YSY, NN, AGV), pp. 982–987.

HPCA-2009-DeOrioWB #design #manycore #memory management #named #validation

Dacota: Post-silicon validation of the memory subsystem in multi-core designs (AD, IW, VB), pp. 405–416.

DAC-2008-AlkabaniMKP #variability

Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability (YA, TM, FK, MP), pp. 606–609.

DAC-2008-BijanskyA #named

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.

DAC-2008-ParkM #analysis #debugging #locality #named

IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors (SBP, SM), pp. 373–378.

DATE-2008-ChakrabortySP #layout #optimisation

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.

DATE-2008-KoN #automation #identification #validation

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation (HFK, NN), pp. 1298–1303.

DATE-2008-KoN08a #automation #generative #on the #validation

On Automated Trigger Event Generation in Post-Silicon Validation (HFK, NN), pp. 256–259.

DAC-2007-KillpackKC #feedback #metric

Silicon Speedpath Measurement and Feedback into EDA flows (KK, CVK, EC), pp. 390–395.

DAC-2007-LiuS #predict #process #scalability #statistics

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations (QL, SSS), pp. 497–502.

DAC-2007-WangBA #correlation #data mining #mining #perspective

Design-Silicon Timing Correlation A Data Mining Perspective (LCW, PB, MSA), pp. 384–389.

DATE-2007-AnisN #architecture #debugging #interactive #low cost #using

Interactive presentation: Low cost debug architecture using lossy compression for silicon debug (EA, NN), pp. 225–230.

DATE-2007-MehraraASCBA #fault #low cost

Low-cost protection for SER upsets and silicon defects (MM, MA, SS, KC, VB, TMA), pp. 1146–1151.

DAC-2006-HsuTJC #debugging

Visibility enhancement for silicon debug (YCH, FST, WJ, YTC), pp. 13–18.

DAC-2006-Josephson #debugging

The good, the bad, and the ugly of silicon debug (DJ), pp. 3–6.

DAC-2006-MajumdarCG #analysis #validation

Hold time validation on silicon and the relevance of hazards in timing analysis (AM, WYC, JG), pp. 326–331.

DAC-2006-Patel

Silicon carrier for computer systems (CSP), pp. 857–862.

DATE-2006-Shrikumar #protocol

40Gbps de-layered silicon protocol engine for TCP record (HS), pp. 188–193.

DAC-2005-BacchiniMDMPSEU #named

ESL: building the bridge between systems to silicon (FB, DM, TD, PM, SAP, SS, SKE, PU), pp. 69–70.

DAC-2004-VermeulenUG #automation #debugging #generative #hardware

Automatic generation of breakpoint hardware for silicon debug (BV, MZU, SKG), pp. 514–517.

DATE-v1-2004-Spirakis #challenge

Opportunities and Challenges in Building Silicon Products in 65nm and Beyond (GS), pp. 2–3.

DATE-v1-2004-Wang #learning #simulation #validation

Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation (LCW), pp. 692–695.

DATE-v2-2004-VrankenSW #layout

Impact of Test Point Insertion on Silicon Area and Timing during Layout (HPEV, FSS, HJW), pp. 810–815.

DAC-2003-HuangC #embedded #framework #using #verification

Using embedded infrastructure IP for SOC post-silicon verification (YH, WTC), pp. 674–677.

DATE-2002-GoossensWPM #network

Networks on Silicon: Combining Best-Effort and Guaranteed Services (KGWG, PW, AMGP, JLvM), pp. 423–425.

DATE-2002-PomeranzRR #debugging #fault

Finding a Common Fault Response for Diagnosis during Silicon Debug (IP, JR, SMR), p. 1116.

ICSM-2002-Ben-Yaacov #quality

Driving Software Quality at a Silicon Valley High-Tech Software Company (GBY), p. 571.

DAC-2001-LeeT #fault #verification

Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System (RL, BT), pp. 822–827.

DATE-2001-QuasemG #fault #simulation

Exact fault simulation for systems on Silicon that protects each core’s intellectual property (MSQ, SKG), p. 804.

DAC-2000-ShepardK #analysis

Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology (KLS, DJK), pp. 239–242.

PLDI-2000-StephensonBA #analysis #compilation

Bitwidth analysis with application to silicon compilation (MS, JB, SPA), pp. 108–120.

DATE-1998-VandenbusscheDLGS #design #interface #specification #top-down

Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.

DATE-1998-X #debugging

Silicon Debug of Systems-on-Chips, pp. 632–633.

HCI-CC-1997-RobertsonB #development

Competence Development in Ten High Tech Companies in Silicon Valley (MMR, GB), pp. 355–359.

DAC-1994-Maly #design #perspective

Cost of Silicon Viewed from VLSI Design Perspective (WM), pp. 135–142.

INTERCHI-1993-Mohageg #research #usability

The silicon graphics customer research and usability group (MM), pp. 465–466.

DAC-1990-ForsytheAYAG #development #simulation

NASFLOW, a Simulation Tool for Silicon Technology Development (DDF, APA, CSY, SA, BG), pp. 333–337.

DAC-1989-PreasPC #automation #hybrid #layout

Automatic Layout of Silicon-on-Silicon Hybrid Packages (BP, MP, DC), pp. 394–399.

DAC-1988-Composano #compilation #design #process

Design Process Model in the Yorktown Silicon Compiler (RC), pp. 489–494.

DAC-1988-HartleyC #compilation

A Digit-Serial Silicon Compiler (RIH, PFC), pp. 646–649.

DAC-1988-OdawaraTHOHO #compilation #interface

A Human Machine Interface for Silicon Compilation (GO, MT, KH, OO, TH, MO), pp. 115–120.

DAC-1987-Elias #case study #compilation #generative #layout #re-engineering

A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (NJE), pp. 82–88.

DAC-1987-JohannsenTM #compilation

An Intelligent Compiler Subsystem for a Silicon Compiler (DLJ, SKT, KM), pp. 443–450.

DAC-1987-SchuckWGK #compilation #design #experience #implementation

The ALGIC Silicon Compiler System: Implementation, Design Experience and Results (JS, NW, MG, GK), pp. 370–375.

DAC-1986-GlesnerSS #compilation #named #statistics #verification

SCAT — a new statistical timing verifier in a silicon compiler system (MG, JS, RBS), pp. 220–226.

DAC-1986-KrekelbergSSL #automation #compilation #layout #synthesis

Automated layout synthesis in the YASC silicon compiler (DEK, ES, GES, LSL), pp. 447–453.

DAC-1986-MarshburnLBCLC #assembly #named

DATAPATH: a CMOS data path silicon assembler (TM, IL, RB, DC, GL, PC), pp. 722–729.

DAC-1986-Solworth #compilation #named

GENERIC: a silicon compiler support language (JAS), pp. 524–530.

DAC-1985-BlackmanFR #compilation

The Silc silicon compiler: language and features (TB, JRF, CR), pp. 232–237.

DAC-1985-FungHK #compilation #design #testing

Design for testability in a silicon compilation environment (HSF, SH, RK), pp. 190–196.

DAC-1985-GrayH

Portability in silicon CAE (JPG, JH), pp. 597–601.

DAC-1985-HealeyG #composition #logic #network

Decomposition of logic networks into silicon (STH, DDG), pp. 162–168.

DAC-1985-KrekelbergSJ #compilation

Yet another silicon compiler (DEK, GES, CSJ), pp. 176–182.

DAC-1985-SteinwegAPN #array #compilation

Silicon compilation of gate array bases (RLS, SJA, KP, SN), pp. 435–438.

DAC-1984-Gajski #compilation

Silicon compilers and expert systems for VLSI (DDG), pp. 86–87.

DAC-1984-MartinezN #compilation

Methodology for compiler generated silicon structures (AM, SN), pp. 689–691.

DAC-1984-WieclawskiP #compilation #layout #network #optimisation

Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler (AW, MAP), pp. 703–704.

POPL-1983-Johnson #code generation

Code Generation for Silicon (SCJ), pp. 14–19.

DAC-1982-GrayBR #array #compilation #design #using

Designing gate arrays using a silicon compiler (JPG, IB, PSR), pp. 377–383.

DAC-1982-Szepieniec #assembly #named

SAGA: An Experimental Silicon Assembler (AAS), pp. 365–370.

DAC-1979-Ayres79a

Silicon compilation-a hierarchical use of PLAs (RA), pp. 314–326.

DAC-1979-Gray #compilation

Introduction to silicon compilation (JPG), pp. 305–306.

DAC-1979-Johannsen #compilation

Bristle Blocks: A silicon compiler (DJ), pp. 310–313.

DAC-1976-DobesB #automation #design #geometry #recognition

The automatic recognition of silicon gate transistor geometries: An LSI design aid program (ID, RB), pp. 327–335.