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Travelled to:
1 × France
Collaborated with:
V.Glöckel J.Fleischmann
Talks about:
transistor (1) parallel (1) circuit (1) partit (1) method (1) simul (1) level (1) vlsi (1) new (1)

Person: Norbert Fröhlich

DBLP DBLP: Fr=ouml=hlich:Norbert

Contributed to:

DATE 20002000

Wrote 1 papers:

DATE-2000-FrohlichGF #clustering #parallel #simulation
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level (NF, VG, JF), pp. 679–684.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.