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Travelled to:
1 × USA
Collaborated with:
R.Y.Chen R.M.Owens M.J.Irwin
Talks about:
architectur (1) techniqu (1) analysi (1) valid (1) power (1) level (1)

Person: Raminder Singh Bajwa

DBLP DBLP: Bajwa:Raminder_Singh

Contributed to:

DAC 19981998

Wrote 1 papers:

DAC-1998-ChenOIB #analysis #architecture #validation
Validation of an Architectural Level Power Analysis Technique (RYC, RMO, MJI, RSB), pp. 242–245.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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