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Travelled to:
1 × Italy
1 × Mexico
1 × Poland
1 × Spain
1 × Sweden
22 × USA
3 × France
5 × Canada
5 × Germany
Collaborated with:
M.T.Kandemir N.Vijaykrishnan R.M.Owens G.Chen J.S.Hu A.Sivasubramaniam Y.Xie S.Srikantaiah F.Li Ö.Özturk I.Kadayif H.Saputra J.Ramanujam D.Duarte H.Mehta W.Zhang Y.Tsai H.S.Kim W.Ye M.S.Park V.Narayanan V.Delaluz S.Kim Y.Zhang A.Gayasen M.Wolczko S.Kim T.Hwang P.Hou J.A.Beekman R.R.Brooks S.Gurumurthi A.Sharifi S.H.K.Narayanan A.J.Ricketts K.M.Irick F.Wang L.Li G.Chen R.Y.Chen R.S.Bajwa M.Borah O.Tickoo R.Iyer S.Kestur J.Sabarad I.Kolcu M.Mutyam W.Hung I.Demirkiran V.De H.Cheng J.Zhan J.Zhao J.Sampson H.Zhao O.Jang W.Ding E.Kultursay T.Zhang T.Yemliha S.P.Muralidhara V.Degalahal B.Mathiske R.Shetty A.Parikh T.Chinoda N.An T.Li L.K.John C.Hsu U.Kremer
Talks about:
energi (12) compil (9) cach (9) power (7) manag (7) level (7) direct (6) optim (6) chip (6) awar (6)

Person: Mary Jane Irwin

DBLP DBLP: Irwin:Mary_Jane

Facilitated 3 volumes:

LCTES 2006Ed
DAC 1999Ed

Contributed to:

DAC 20152015
DATE 20152015
DAC 20122012
DATE 20122012
HPCA 20112011
LCTES 20102010
PLDI 20102010
ASPLOS 20082008
DATE 20062006
LCTES 20062006
PLDI 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
HPCA 20042004
ISMM 20042004
LCTES 20042004
CC 20032003
DAC 20032003
DATE 20032003
LCTES 20032003
OOPSLA 20032003
DAC 20022002
DATE 20022002
HPCA 20022002
DAC 20012001
HPCA 20012001
LCTES/OM 20012001
PASTE 20012001
VLDB 20012001
DAC 20002000
LCTES 20002000
DAC 19981998
DAC 19961996
DAC 19951995
DAC 19921992
DAC 19891989
DAC 19881988
DAC 19871987

Wrote 56 papers:

Core vs. uncore: the heart of darkness (HYC, JZ, JZ, YX, JS, MJI), p. 6.
DATE-2015-ParkTNII #performance #platform
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system (MSP, OT, VN, MJI, RI), pp. 1503–1508.
DAC-2012-SharifiSKI #capacity
Courteous cache sharing: being nice to others in capacity management (AS, SS, MTK, MJI), pp. 678–687.
DAC-2012-ZhaoJDZKI #design #hybrid #multi #optimisation
A hybrid NoC design for cache coherence optimization for chip multiprocessors (HZ, OJ, WD, YZ, MTK, MJI), pp. 834–842.
DATE-2012-ParkKSNI #classification
An FPGA-based accelerator for cortical object classification (MSP, SK, JS, VN, MJI), pp. 691–696.
HPCA-2011-SrikantaiahKZKIX #adaptation #configuration management #multi #named
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy (SS, EK, TZ, MTK, MJI, YX), pp. 231–242.
LCTES-2010-OzturkKIN #compilation #multi #reliability
Compiler directed network-on-chip reliability enhancement for chip multiprocessors (ÖÖ, MTK, MJI, SHKN), pp. 85–94.
PLDI-2010-KandemirYMSIZ #multi
Cache topology aware computation mapping for multicores (MTK, TY, SPM, SS, MJI, YZ), pp. 74–85.
ASPLOS-2008-SrikantaiahKI #adaptation #multi #set
Adaptive set pinning: managing shared caches in chip multiprocessors (SS, MTK, MJI), pp. 135–144.
DATE-2006-KandemirCLIK #clustering #process
Activity clustering for leakage management in SPMs (MTK, GC, FL, MJI, IK), pp. 696–697.
DATE-2006-RickettsIVI #scheduling
Priority scheduling in digital microfluidics-based biochips (AJR, KMI, NV, MJI), pp. 329–334.
DATE-2006-WangXVI #analysis #optimisation
On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.
LCTES-2006-MutyamLNKI #functional
Compiler-directed thermal management for VLIW functional units (MM, FL, NV, MTK, MJI), pp. 163–172.
PLDI-2006-ChenLKI #energy #scalability
Reducing NoC energy consumption through compiler-directed channel voltage scaling (GC, FL, MTK, MJI), pp. 193–203.
Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
DATE-2005-HuLDKVI #detection #fault
Compiler-Directed Instruction Duplication for Soft Error Detection (JSH, FL, VD, MTK, NV, MJI), pp. 1056–1057.
DATE-2005-HungXVKI #embedded #scheduling
Thermal-Aware Task Allocation and Scheduling for Embedded Systems (WLH, YX, NV, MTK, MJI), pp. 898–899.
DATE-2005-OzturkKI #garbage collection #named
BB-GC: Basic-Block Level Garbage Collection (ÖÖ, MTK, MJI), pp. 1032–1037.
DATE-2005-TsaiVXI #network
Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DAC-2004-OzturkKDCI #behaviour
Data compression for improving SPM behavior (ÖÖ, MTK, ID, GC, MJI), pp. 401–406.
DATE-v1-2004-HuVKKI #reduction #reuse #scheduling
Scheduling Reusable Instructions for Power Reduction (JSH, NV, SK, MTK, MJI), pp. 148–155.
A Crosstalk Aware Interconnect with Variable Cycle Transmission (LL, NV, MTK, MJI), pp. 102–107.
HPCA-2004-HuVI #scheduling
Exploring Wakeup-Free Instruction Scheduling (JSH, NV, MJI), pp. 232–243.
ISMM-2004-ChenKVI #analysis #embedded #java #optimisation
Field level analysis for heap space optimization in embedded java environments (GC, MTK, NV, MJI), pp. 131–142.
LCTES-2004-SaputraCBVKI #embedded
Code protection for resource-constrained embedded devices (HS, GC, RRB, NV, MTK, MJI), pp. 240–248.
Address Register Assignment for Reducing Code Size (MTK, MJI, GC, JR), pp. 273–289.
DAC-2003-TsaiDVI #reduction #scalability
Implications of technology scaling on leakage reduction techniques (YFT, DD, NV, MJI), pp. 187–190.
DATE-2003-SaputraVKIBKZ #behaviour #encryption #energy
Masking the Energy Behavior of DES Encryption (HS, NV, MTK, MJI, RRB, SK, WZ), pp. 10084–10089.
DATE-2003-ZhangKVID #compilation #energy
Compiler Support for Reducing Leakage Energy Consumption (WZ, MTK, NV, MJI, VD), pp. 11146–11147.
LCTES-2003-KimVKI #adaptation #architecture #optimisation #parallel
Adapting instruction level parallelism for optimizing leakage in VLIW architectures (HSK, NV, MTK, MJI), pp. 275–283.
OOPSLA-2003-ChenKVIMW #java
Heap compression for memory-constrained Java environments (GC, MTK, NV, MJI, BM, MW), pp. 282–301.
DAC-2002-DelaluzSKVI #energy
Scheduler-based DRAM energy management (VD, AS, MTK, NV, MJI), pp. 697–702.
DATE-2002-DuarteVI #power management
A Complete Phase-Locked Loop Power Consumption Model (DD, NV, MJI), p. 1108.
DATE-2002-HuVKI #power management
Power-Efficient Trace Caches (JSH, NV, MTK, MJI), p. 1091.
DATE-2002-KadayifKVIS #compilation #energy #estimation #framework #named #optimisation
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization (IK, MTK, NV, MJI, AS), pp. 436–442.
HPCA-2002-ChenSKVIW #embedded #garbage collection #java
Tuning Garbage Collection in an Embedded Java Environment (GC, RS, MTK, NV, MJI, MW), pp. 92–103.
HPCA-2002-GurumurthiSIVKLJ #approach #estimation #simulation #using
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach (SG, AS, MJI, NV, MTK, TL, LKJ), pp. 141–150.
LCTES-SCOPES-2002-HuKVISZ #morphism #polymorphism
Compiler-directed cache polymorphism (JSH, MTK, NV, MJI, HS, WZ), pp. 165–174.
LCTES-SCOPES-2002-SaputraKVIHHK #compilation #energy #scalability
Energy-conscious compilation based on voltage scaling (HS, MTK, NV, MJI, JSH, CHH, UK), pp. 2–11.
DAC-2001-KandemirRIVKP #memory management
Dynamic Management of Scratch-Pad Memory Space (MTK, JR, MJI, NV, IK, AP), pp. 690–695.
HPCA-2001-DelaluzKVSI #energy #hardware #using
DRAM Energy Management Using Software and Hardware Directed Power Mode Control (VD, MTK, NV, AS, MJI), pp. 159–169.
LCTES-OM-2001-KadayifKVIR #architecture
Morphable Cache Architectures: Potential Benefits (IK, MTK, NV, MJI, JR), pp. 128–137.
PASTE-2001-KadayifCKVIS #energy #named
vEC: virtual energy counters (IK, TC, MTK, NV, MJI, AS), pp. 28–31.
VLDB-2001-AnSVKIG #behaviour #data access #energy
Analyzing energy behavior of spatial access methods for memory-resident data (NA, AS, NV, MTK, MJI, SG), pp. 411–420.
DAC-2000-KandemirVIY #compilation #optimisation
Influence of compiler optimizations on system power (MTK, NV, MJI, WY), pp. 304–307.
DAC-2000-YeVKI #design #energy #estimation #using
The design and use of simplepower: a cycle-accurate energy estimation tool (WY, NV, MTK, MJI), pp. 340–345.
LCTES-2000-KandemirVIK #energy #towards
Towards Energy-Aware Iteration Space Tiling (MTK, NV, MJI, HSK), pp. 211–215.
DAC-1998-ChenOIB #analysis #architecture #validation
Validation of an Architectural Level Power Analysis Technique (RYC, RMO, MJI, RSB), pp. 242–245.
DAC-1996-MehtaOI #clustering #energy
Energy Characterization based on Clustering (HM, RMO, MJI), pp. 702–707.
DAC-1995-MehtaBOI #estimation #process
Accurate Estimation of Combinational Circuit Activity (HM, MB, RMO, MJI), pp. 618–622.
DAC-1992-KimOI #generative #performance
Experiments with a Performance Driven Module Generator (SK, RMO, MJI), pp. 687–690.
DAC-1989-HwangOI #communication #complexity #logic #multi #synthesis #using
Multi-Level Logic Synthesis Using Communication Complexity (TH, RMO, MJI), pp. 215–220.
DAC-1989-IrwinO #2d #comparison #layout #matrix #tool support
A Comparison of Four Two-dimensional Gate Matrix Layout Tools (MJI, RMO), pp. 698–701.
DAC-1988-HouOI #named
DECOMPOSER: A Synthesizer for Systolic Systems (PPH, RMO, MJI), pp. 650–653.
DAC-1987-BeekmanOI #array #generative #performance
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation (JAB, RMO, MJI), pp. 357–362.
DAC-1987-OwensI #design #overview
An Overview of the Penn State Design System (RMO, MJI), pp. 516–522.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.