BibSLEIGH — Proceedings of the 35th Design Automation Conference

Basant R. Chawla, Randal E. Bryant, Jan M. Rabaey
Proceedings of the 35th Design Automation Conference
DAC, 1998.

SYS

@proceedings{DAC-1998,
	acmid         = "277044",
	address       = "San Francico, California, USA",
	editor        = "Basant R. Chawla and Randal E. Bryant and Jan M. Rabaey",
	isbn          = "0-89791-964-5",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 35th Design Automation Conference}",
	year          = 1998,
}

Contents (147 items)

DAC-1998-KishinevskyCK #analysis #interface #specification #synthesis: Asynchronous Interface Specification, Analysis and Synthesis (MK, JC, AK), pp. 2–7.
DAC-1998-PasseroneRS #automation #interface #protocol #synthesis: Automatic Synthesis of Interfaces Between Incompatible Protocols (RP, JAR, ALSV), pp. 8–13.
DAC-1998-SmithM #automation #component #composition #hardware: Automated Composition of Hardware Components (JS, GDM), pp. 14–19.
DAC-1998-ChouW #equation #multi #parametricity: Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC’s (MC, JW), pp. 20–25.
DAC-1998-DemirMR: Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation (AD, AM, JSR), pp. 26–31.
DAC-1998-CarroN #adaptation #algorithm #performance: Efficient Analog Test Methodology Based on Adaptive Algorithms (LC, MN), pp. 32–37.
DAC-1998-ArsintescuCMCK #constraints: General AC Constraint Transformation for Analog ICs (BGA, EC, EM, UC, WHK), pp. 38–43.
DAC-1998-RaelRA #design: Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver (JR, AR, AAA), pp. 44–49.
DAC-1998-HilgenstockHONP #multi #video: A Video Signal Processor for MIMD Multiprocessing (JH, KH, JO, DN, PP), pp. 50–55.
DAC-1998-WittenburgHKOBLKP #image #parallel #performance #programmable: Realization of a Programmable Parallel DSP for High Performance Image Processing Applications (JPW, WH, JK, MO, MB, HL, HK, PP), pp. 56–61.
DAC-1998-SuttonSR #multi #using: A Multiprocessor DSP System Using PADDI-2 (RAS, VPS, JMR), pp. 62–65.
DAC-1998-GrbicBCGGLLMSSVZ #design #implementation #multi: Design and Implementation of the NUMAchine Multiprocessor (AG, SDB, SC, RG, MG, GGL, KL, NM, SS, MS, ZGV, ZZ), pp. 66–69.
DAC-1998-YoungMSTHN #design #embedded #java #refinement #specification #using: Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement (JSY, JM, MS, AT, PNH, ARN), pp. 70–75.
DAC-1998-SilvaYMCWJCVSM #data transfer #performance #synthesis: Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer (JLdSJ, CYC, MM, KC, SW, GGdJ, FC, DV, PS, HDM), pp. 76–81.
DAC-1998-KarkowskiC #algorithm #design #embedded #multi: Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design (IK, HC), pp. 82–87.
DAC-1998-ChouB #composition #distributed #embedded #process #towards: Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems (PHC, GB), pp. 88–93.
DAC-1998-Shepard #design: Design Methodologies for Noise in Digital Integrated Circuits (KLS), pp. 94–99.
DAC-1998-LakshminarayanaJ #behaviour #control flow #framework #named #optimisation #throughput: FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions (GL, NKJ), pp. 102–107.
DAC-1998-LakshminarayanaRJ #behaviour #control flow #execution #scheduling: Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions (GL, AR, NKJ), pp. 108–113.
DAC-1998-TarafdarL #data transfer #synthesis #using: The DT-Model: High-Level Synthesis Using Data Transfers (ST, ML), pp. 114–117.
DAC-1998-OhH #data flow #design #graph: Rate Optimal VLSI Design from Data Flow Graph (MO, SH), pp. 118–121.
DAC-1998-OttenB #performance: Planning for Performance (RHJMO, RKB), pp. 122–127.
DAC-1998-SalekLP #design: A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together (AHS, JL, MP), pp. 128–134.
DAC-1998-SuttonD #approach #framework: Framework Encapsulations: A New Approach to CAD Tool Interoperability (PRS, SWD), pp. 134–139.
DAC-1998-HinesB #design #distributed #embedded #framework #validation: A Geographically Distributed Framework for Embedded System Design and Validation (KH, GB), pp. 140–145.
DAC-1998-ChanSN #design #named: WELD — An Environment for Web-based Electronic Design (FLC, MDS, ARN), pp. 146–151.
DAC-1998-FallahDK98a #functional #metric #named #performance #test coverage #verification: OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification (FF, SD, KK), pp. 152–157.
DAC-1998-GrinwaldHOUZ #design #tool support #verification: User Defined Coverage — A Tool Supported Methodology for Design Verification (RG, EH, MO, SU, AZ), pp. 158–163.
DAC-1998-Marantz #functional #performance #re-engineering #verification: Enhanced Visibility and Performance in Functional Verification by Reconstruction (JM), pp. 164–169.
DAC-1998-KimCLLPK #functional #modelling: Virtual Chip: Making Functional Models Work on Real Target Systems (NK, HC, SL, SL, ICP, CMK), pp. 170–173.
DAC-1998-HongKQPS #optimisation: Power Optimization of Variable Voltage Core-Based Systems (IH, DK, GQ, MP, MBS), pp. 176–181.
DAC-1998-PaleologoBBM #optimisation #policy #power management: Policy Optimization for Dynamic Power Management (GAP, LB, AB, GDM), pp. 182–187.
DAC-1998-LiH #embedded #energy #estimation #framework: A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems (YL, JH), pp. 188–193.
DAC-1998-ZhongAMM #case study #configuration management #problem #satisfiability #using: Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability (PZ, PA, SM, MM), pp. 194–199.
DAC-1998-DrechslerDG #performance: Fast Exact Minimization of BDDs (RD, ND, WG), pp. 200–205.
DAC-1998-HinsbergerK #library #scalability: Boolean Matching for Large Libraries (UH, RK), pp. 206–211.
DAC-1998-ShiLKY #3d #algorithm #performance: A Fast Hierarchical Algorithm for 3-D Capacitance Extraction (WS, JL, NK, TY), pp. 212–217.
DAC-1998-DengiR #2d #bound #megamodelling: Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction (EAD, RAR), pp. 218–223.
DAC-1998-ZhaoDKL #3d #performance: Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green’s Functions (JZ, WWMD, SK, DEL), pp. 224–229.
DAC-1998-NassifDH #modelling #robust #verification: Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
DAC-1998-McGrawAK #design #pipes and filters #top-down: A Top-Down Design Environment for Developing Pipelined Datapaths (RMM, JHA, RHK), pp. 236–241.
DAC-1998-ChenOIB #analysis #architecture #validation: Validation of an Architectural Level Power Analysis Technique (RYC, RMO, MJI, RSB), pp. 242–245.
DAC-1998-HattoriNSNUTS #design: Design Methodology of a 200MHz Superscalar Microprocessor: SH-4 (TH, YN, MS, SN, KU, TT, RS), pp. 246–249.
DAC-1998-VecianaJG #algorithm #constraints #performance #probability: Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance (GdV, MFJ, JHG), pp. 251–256.
DAC-1998-KalavadeM #embedded #estimation #performance: A Tool for Performance Estimation of Networked Embedded End-systems (AK, PM), pp. 257–262.
DAC-1998-DasdanRG #embedded #realtime: Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems (AD, DR, RKG), pp. 263–268.
DAC-1998-EisenmannJ: Generic Global Placement and Floorplanning (HE, FMJ), pp. 269–274.
DAC-1998-ParakhBS #polynomial: Congestion Driven Quadratic Placement (PNP, RBB, KAS), pp. 275–278.
DAC-1998-WangBS #named #semistructured data: Potential-NRG: Placement with Incomplete Data (MW, PB, MS), pp. 279–282.
DAC-1998-FangW #clustering #functional #multi #replication #using: Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication (WJF, ACHW), pp. 283–286.
DAC-1998-OhP #design #multi #network: Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce (JO, MP), pp. 287–290.
DAC-1998-LiK #layout #verification: Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.
DAC-1998-MarquesKWS #3d #modelling #performance: A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects (NAM, MK, JW, LMS), pp. 297–302.
DAC-1998-KrauterM #analysis #layout: Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis (BK, SM), pp. 303–308.
DAC-1998-GuerraPR #behaviour #optimisation: A Methodology for Guided Behavioral-Level Optimization (LMG, MP, JMR), pp. 309–314.
DAC-1998-SchaumontVREB #design #programming: A Programming Environment for the Design of Complex High Speed ASICs (PS, SV, LR, ME, IB), pp. 315–320.
DAC-1998-LeeKPM #architecture #multi #programmable: Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor (CL, JK, MP, WHMS), pp. 321–326.
DAC-1998-Dill #question #simulation #verification #what: What’s Between Simulation and Formal Verification? (DLD), pp. 328–329.
DAC-1998-CongW #performance: Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (JC, CW), pp. 330–335.
DAC-1998-KravetsS #logic #multi #named #synthesis: M32: A Constructive multilevel Logic Synthesis System (VNK, KAS), pp. 336–341.
DAC-1998-ChangC #performance: Efficient Boolean Division and Substitution (SCC, DIC), pp. 342–347.
DAC-1998-KukimotoBS #graph: Delay-Optimal Technology Mapping by DAG Covering (YK, RKB, PS), pp. 348–351.
DAC-1998-Kung #algorithm #library #optimisation #performance: A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries (DSK), pp. 352–355.
DAC-1998-CongM #design #multi #performance: Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs (JC, PHM), pp. 356–361.
DAC-1998-AlpertDQ #optimisation: Buffer Insertion for Noise and Delay Optimization (CJA, AD, STQ), pp. 362–367.
DAC-1998-LillisB: Table-Lookup Methods for Improved Performance-Driven Routing (JL, PB), pp. 368–373.
DAC-1998-ZhouW #constraints: Global Routing with Crosstalk Constraints (HZ, DFW), pp. 374–377.
DAC-1998-TsengSS: Timing and Crosstalk Driven Area Routing (HPT, LS, CS), pp. 378–381.
DAC-1998-LokanathanB #multi #optimisation #process: Process Multi-Circuit Optimization (ANL, JBB), pp. 382–387.
DAC-1998-PandaDENB #design #incremental #migration #named: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization (RP, AD, TE, JN, DB), pp. 388–391.
DAC-1998-CuletuAM: A Practical Repeater Insertion Method in High Speed VLSI Circuits (JC, CA, JM), pp. 392–395.
DAC-1998-IenneG #case study #design #experience #question #standard #tool support: Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? (PI, AG), pp. 396–401.
DAC-1998-OrshanskyCH #performance #simulation #statistics: A Statistical Performance Simulation Methodology for VLSI Circuits (MO, JCC, CH), pp. 402–407.
DAC-1998-Razavi #challenge #design: RF IC Design Challenges (BR), pp. 408–413.
DAC-1998-DunlopDFKLMR #design #tool support: Tools and Methodology for RF IC Design (AD, AD, PF, SK, DEL, RCM, JSR), pp. 414–420.
DAC-1998-Yuan #modelling #network #simulation: Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards (FYY), pp. 421–426.
DAC-1998-KirovskiP #graph #performance #scalability: Efficient Coloring of a Large Spectrum of Graphs (DK, MP), pp. 427–432.
DAC-1998-KimJT #optimisation #using: Arithmetic Optimization Using Carry-Save-Adders (TK, WJ, SWKT), pp. 433–438.
DAC-1998-LakshminarayanaJ98a #behaviour #power management #synthesis: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions (GL, NKJ), pp. 439–444.
DAC-1998-RaviMSS #approximate #composition #diagrams: Approximation and Decomposition of Binary Decision Diagrams (KR, KLM, TRS, FS), pp. 445–450.
DAC-1998-GovindarajuDHH #approximate #reachability #using: Approximate Reachability with BDDs Using Overlapping Projections (SGG, DLD, AJH, MH), pp. 451–456.
DAC-1998-PardoH #incremental #model checking #using: Incremental CTL Model Checking Using BDD Subsetting (AP, GDH), pp. 457–462.
DAC-1998-KayP #named #probability: PRIMO: Probability Interpretation of Moments for Delay Calculation (RK, LTP), pp. 463–468.
DAC-1998-LiuPS #modelling #named #order: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (YL, LTP, AJS), pp. 469–472.
DAC-1998-LiuC: Extending Moment Computation to 2-Port Circuit Representations (FJL, CKC), pp. 473–476.
DAC-1998-NguyenDN #linear #simulation: Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation (TVN, AD, OJN), pp. 477–482.
DAC-1998-UsamiIIKTHATK #design #power management #scalability: Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques (KU, MI, TI, MK, MT, MH, HA, TT, TK), pp. 483–488.
DAC-1998-WeiCJRD #design #optimisation #performance: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.
DAC-1998-KaoNC: MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns (JK, SN, AC), pp. 495–500.
DAC-1998-Lin #concurrent #source code #synthesis: Software Synthesis of Process-Based Concurrent Programs (BL), pp. 502–505.
DAC-1998-HongBLS #embedded: Don’t Care-Based BDD Minimization for Embedded Software (YH, PAB, LL, ES), pp. 506–509.
DAC-1998-HanonoD #code generation #resource management #scheduling: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator (SH, SD), pp. 510–515.
DAC-1998-LekatsasW #embedded: Code Compression for Embedded Systems (HL, WW), pp. 516–521.
DAC-1998-BarrettDL: A Decision Procedure for Bit-Vector Arithmetic (CWB, DLD, JRL), pp. 522–527.
DAC-1998-FallahDK #functional #generative #linear #modelling #programming #satisfiability #using: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability (FF, SD, KK), pp. 528–533.
DAC-1998-WangAK #array #automation #evaluation #generative #using #verification: Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation (LCW, MSA, NK), pp. 534–537.
DAC-1998-AagaardJS #evaluation #industrial #proving #theorem proving: Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment (MA, RBJ, CJHS), pp. 538–541.
DAC-1998-GhoshDJ #low cost #performance #testing: A Fast and Low Cost Testing Technique for Core-Based System-on-Chip (IG, SD, NKJ), pp. 542–547.
DAC-1998-ParulkarGB #behaviour: Introducing Redundant Computations in a Behavior for Reducing BIST Resources (IP, SKG, MAB), pp. 548–553.
DAC-1998-GhoshJB #analysis #testing: A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis (IG, NKJ, SB), pp. 554–559.
DAC-1998-IsmailFN: Figures of Merit to Characterize the Importance of On-Chip Inductance (YII, EGF, JLN), pp. 560–565.
DAC-1998-MassoudMBW #layout: Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
DAC-1998-NagarajCHY #analysis #approach: A Practical Approach to Static Signal Electromigration Analysis (NSN, FC, HH, DY), pp. 572–577.
DAC-1998-KukimotoB #analysis #functional: Hierarchical Functional Timing Analysis (YK, RKB), pp. 580–585.
DAC-1998-AmonBL #using: Making Complex Timing Relationships Readable: Presburger Formula Simplicication Using Don’t Cares (TA, GB, JL), pp. 586–590.
DAC-1998-NemaniN #estimation #perspective: Delay Estimation VLSI Circuits from a High-Level View (MN, FNN), pp. 591–594.
DAC-1998-DartuP #analysis #named: TETA: Transistor-Level Engine for Timing Analysis (FD, LTP), pp. 595–598.
DAC-1998-YangD #validation: Validation with Guided Search of the State Space (CHY, DLD), pp. 599–604.
DAC-1998-XieB #classification #finite #markov #performance: Efficient State Classification of Finite State Markov Chains (AX, PAB), pp. 605–610.
DAC-1998-HasteerMB #algorithm #automaton #verification: An Implicit Algorithm for Finding Steady States and its Application to FSM Verification (GH, AM, PB), pp. 611–614.
DAC-1998-AzizKS #hybrid #simulation #using #verification: Hybrid Verification Using Saturated Simulation (AA, JHK, TRS), pp. 615–618.
DAC-1998-SunVJ #performance #verification: Fast State Verification (DS, BV, WJ), pp. 619–624.
DAC-1998-El-MalehKR #learning #performance: A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance (AHEM, MK, JR), pp. 625–631.
DAC-1998-HuangCCL #design #fault: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
DAC-1998-TaylorQBDHHR #functional #multi #verification: Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor — The DEC Alpha 21264 Microprocessor (SAT, MQ, DB, ND, SH, JH, CR), pp. 638–643.
DAC-1998-MalkaZ #analysis #debugging #design #estimation #reliability #statistics: Design Reliability — Estimation through Statistical Analysis of Bug Discovery Data (YM, AZ), pp. 644–649.
DAC-1998-EvansSVBDHHL #functional #scalability #verification: Functional Verification of Large ASICs (AE, AS, GV, TB, MD, GH, TH, YL), pp. 650–655.
DAC-1998-OlukotunHO #simulation: Digital System Simulation: Methodologies and Examples (KO, MH, DO), pp. 658–663.
DAC-1998-LuoWA #functional #hybrid #performance #simulation: Hybrid Techniques for Fast Functional Simulation (YL, TW, AA), pp. 664–667.
DAC-1998-BauerBKV #configuration management #logic #performance #simulation: A Reconfigurable Logic Machine for Fast Event-Driven Simulation (JB, MB, IK, PV), pp. 668–671.
DAC-1998-KimB #algorithm #estimation #parallel: Parallel Algorithms for Power Estimation (VK, PB), pp. 672–677.
DAC-1998-ChenR #megamodelling: A Power Macromodeling Technique Based on Power Sensitivity (ZC, KR), pp. 678–683.
DAC-1998-QiuWP #estimation #order #statistics #using: Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics (QQ, QW, MP), pp. 684–689.
DAC-1998-KwakP #estimation #fault #logic #statistics: An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits (BK, ESP), pp. 690–693.
DAC-1998-MurgaiFO #using: Using Complementation and Resequencing to Minimize Transitions (RM, MF, ALO), pp. 694–697.
DAC-1998-AndersonB #scalability: Technology Mapping for Large Complex PLDs (JHA, SDB), pp. 698–703.
DAC-1998-CongX: Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (JC, SX), pp. 704–707.
DAC-1998-KorupoluLW #independence #logic: Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs (MRK, KKL, DFW), pp. 708–711.
DAC-1998-JiangJH #composition #encoding #synthesis: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis (JHRJ, JYJ, JDH), pp. 712–717.
DAC-1998-KumthekarBMS #optimisation: In-Place Power Optimization for LUT-Based FPGAs (BK, LB, EM, FS), pp. 718–721.
DAC-1998-HwangCH #approach #design #power management #re-engineering #using: A Re-engineering Approach to Low Power FPGA Design Using SPFD (JMH, FYC, TH), pp. 722–725.
DAC-1998-GowanBJ #design: Power Considerations in the Design of the Alpha 21264 Microprocessor (MKG, LLB, DBJ), pp. 726–731.
DAC-1998-TiwariSRMPB: Reducing Power in High-Performance Microprocessors (VT, DS, SR, GM, RP, FB), pp. 732–737.
DAC-1998-DharchoudhuryPBVTB #analysis #design #network: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
DAC-1998-SteeleORH #verification: Full-Chip Verification Methods for DSM Power Distribution Systems (GS, DO, SR, SZH), pp. 744–749.
DAC-1998-Zorian: System-Chip Test Strategies (YZ), pp. 752–757.
DAC-1998-MonteiroO #composition #finite #power management #state machine: Finite State Machine Decomposition For Low Power (JCM, ALO), pp. 758–763.
DAC-1998-BeniniMLMOP #kernel #optimisation: Computational Kernels and their Application to Sequential Power Optimization (LB, GDM, AL, EM, GO, MP), pp. 764–769.
DAC-1998-SeawrightM #clustering #optimisation: Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions (AS, WM), pp. 770–775.
DAC-1998-KahngLMMMPTWW: Watermarking Techniques for Intellectual Property Protection (ABK, JL, WHMS, SM, ILM, MP, PT, HW, GW), pp. 776–781.
DAC-1998-KahngMMPTWW #design #physics #robust: Robust IP Watermarking Methodologies for Physical Design (ABK, SM, ILM, MP, PT, HW, GW), pp. 782–787.
DAC-1998-HauckK #security: Data Security for Web-based CAD (SH, SK), pp. 788–793.
DAC-1998-HoltmannB #compilation #design #protocol #using: Design of a SPDIF Receiver Using Protocol Compiler (UH, PB), pp. 794–799.
DAC-1998-YangKNCSRKLLKYKLHKKPPLHPK #development #named: MetaCore: An Application Specific DSP Development System (JHY, BWK, SJN, JHC, SWS, CHR, YSK, DHL, JYL, JSK, HDY, JYK, KML, CSH, IHK, JSK, KIP, KHP, YHL, SHH, ICP, CMK), pp. 800–803.
DAC-1998-CuattoPLJDSS #case study #design #embedded: A Case Study in Embedded System Design: An Engine Control Unit (TC, CP, LL, AJ, AD, CS, ALSV), pp. 804–807.
DAC-1998-AlbrechtNR #benchmark #design #embedded #estimation #metric #performance: HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design (TWA, JN, SR), pp. 808–811.
DAC-1998-GajskiVNG: System-level exploration with SpecSyn (DG, FV, SN, JG), pp. 812–817.

Basant R. Chawla, Randal E. Bryant, Jan M. RabaeyProceedings of the 35th Design Automation ConferenceDAC, 1998.

Contents (147 items)

Basant R. Chawla, Randal E. Bryant, Jan M. Rabaey
Proceedings of the 35th Design Automation Conference
DAC, 1998.