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Collaborated with:
A.R.Helland
Talks about:
transmiss (1) mismatch (1) reflect (1) control (1) signal (1) effect (1) analyz (1) speed (1) simul (1) logic (1)

Person: Robert E. Canright

DBLP DBLP: Canright:Robert_E=

Contributed to:

DAC 19871987
DAC 19861986

Wrote 2 papers:

DAC-1987-CanrightH #logic
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic (REC, ARH), pp. 133–139.
DAC-1986-Canright #simulation
Simulating and controlling the effects of transmission line impedance mismatches (REC), pp. 778–785.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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