BibSLEIGH — Proceedings of the 23rd Design Automation Conference

Don Thomas
Proceedings of the 23rd Design Automation Conference
DAC, 1986.

SYS

@proceedings{DAC-1986,
	acmid         = "318013",
	editor        = "Don Thomas",
	publisher     = "{IEEE Computer Society Press}",
	title         = "{Proceedings of the 23rd Design Automation Conference}",
	year          = 1986,
}

Contents (122 items)

DAC-1986-Williams #automation #design #industrial: IBM perspectives on the electrical design automation industry (RMW), p. 1.
DAC-1986-Smith #logic #parallel #simulation: Fundamentals of parallel logic simulation (RJSI), pp. 2–12.
DAC-1986-WongFCS #logic #simulation #statistics: Statistics on logic simulation (KFW, MAF, RDC, BLS), pp. 13–19.
DAC-1986-Frank #parallel #simulation: Exploiting parallelism in a switch-level simulation machine (EHF), pp. 20–26.
DAC-1986-KatzAC #design: A version server for computer-aided design data (RHK, MA, EEC), pp. 27–33.
DAC-1986-RieuN #database #semantics: Semantics of CAD objects for generalized databases (DR, GTN), pp. 34–40.
DAC-1986-WeissRRG #design #named: DOSS: a storage system for design data (SW, KR, TR, AG), pp. 41–47.
DAC-1986-KnappP #design: A design utility manager: the ADAM planning engine (DK, ACP), pp. 48–54.
DAC-1986-BushnellD #integration #tool support #using: VLSI CAD tool integration using the Ulysses environment (MLB, SWD), pp. 55–61.
DAC-1986-BrewerG #design #paradigm: An expert-system paradigm for design (FB, DG), pp. 62–68.
DAC-1986-HancockD #automation #design #parallel #tutorial: Tutorial on parallel processing for design automation applications (JMH, SD), pp. 69–77.
DAC-1986-Geus #automation #benchmark #design #logic #metric #optimisation #synthesis: Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference (AJdG), p. 78.
DAC-1986-GregoryBGH #automation #logic #named #optimisation: SOCRATES: a system for automatically synthesizing and optimizing combinational logic (DG, KAB, AJdG, GDH), pp. 79–85.
DAC-1986-Sasao #generative #multi #named #synthesis #using: MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators (TS), pp. 86–93.
DAC-1986-JoynerTBNG #adaptation #logic #synthesis: Technology adaption in logic synthesis (WHJJ, LT, DB, TAN, SCG), pp. 94–100.
DAC-1986-WongL #algorithm #design: A new algorithm for floorplan design (DFW, CLL), pp. 101–107.
DAC-1986-BhaskerS #algorithm #graph #linear: A linear algorithm to find a rectangular dual of a planar triangulated graph (JB, SS), pp. 108–114.
DAC-1986-ShinSS #2d: Two-dimensional compaction by “zone refining” (HS, ALSV, CHS), pp. 115–122.
DAC-1986-LinA #bound #layout #named: Minplex — a compactor that minimizes the bounding rectangle and individual rectangles in a layout (SLL, JA), pp. 123–130.
DAC-1986-VenkataramanW #automation #layout #named: GEMS: an automatic layout tool for MIMOLA schematics (VVV, CDW), pp. 131–137.
DAC-1986-SugimotoAKK #development #object-oriented #visual notation: An object-oriented visual simulator for microprogram development (AS, SA, MK, YK), pp. 138–144.
DAC-1986-Janni #monitoring: A monitor for complex CAD systems (ADJ), pp. 145–151.
DAC-1986-HammerRRHT #automation #generative #interactive #interface: Automating the generation of interactive interfaces (KH, DR, TR, JH, TT), pp. 152–158.
DAC-1986-Adler #multi #named: SIMMOS: a multiple-delay switch-level simulator (DA), pp. 159–163.
DAC-1986-BarzilaiBHIS #analysis #fault #named #performance #verification: SLS — a fast switch level simulator for verification and fault coverage analysis (ZB, DKB, LMH, VSI, GMS), pp. 164–170.
DAC-1986-Beckett #c #modelling #network: MOS circuit models in Network C (WSB), pp. 171–178.
DAC-1986-VidigalND #analysis #integration #named #network: CINNAMON: coupled integration and nodal analysis of MOS networks (LMV, SRN, SWD), pp. 179–185.
DAC-1986-OdrynaNC: A workstation-mixed model circuit simulator (PO, KN, CC), pp. 186–192.
DAC-1986-KuoC #generative #multi: Generating essential primes for a Boolean function with multiple-valued inputs (YSK, WKC), pp. 193–199.
DAC-1986-SupowitF #verification: A new method for verifying sequential circuits (KJS, SJF), pp. 200–207.
DAC-1986-OdawaraTOOZ #comparison #logic #verification: A logic verifier based on Boolean comparison (GO, MT, OO, TO, ZqZ), pp. 208–214.
DAC-1986-BapatV #logic #reasoning #using: Reasoning about digital systems using temporal logic (SB, GV), pp. 215–219.
DAC-1986-GlesnerSS #compilation #named #statistics #verification: SCAT — a new statistical timing verifier in a silicon compiler system (MG, JS, RBS), pp. 220–226.
DAC-1986-HwangKN #modelling #verification: An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.
DAC-1986-WeiweiX #algorithm #fault #generative #robust #testing: Robust test generation algorithm for stuck-open fault in CMOS circuits (WM, XL), pp. 236–242.
DAC-1986-ShihA #generative #physics #testing: Transistor-level test generation for physical failures in CMOS circuits (HCS, JAA), pp. 243–249.
DAC-1986-Marlett #effectiveness #generative #testing: An effective test generation system for sequential circuits (RM), pp. 250–256.
DAC-1986-BarclayA #algorithm #generative #heuristic #testing: A heuristic chip-level test generation algorithm (DSB, JRA), pp. 257–262.
DAC-1986-PaulinKG #approach #automation #multi #named #synthesis: HAL: a multi-paradigm approach to automatic data path synthesis (PGP, JPK, EFG), pp. 263–270.
DAC-1986-Marwedel #synthesis: A new synthesis for the MIMOLA software system (PM), pp. 271–277.
DAC-1986-Peng #design #synthesis: Synthesis of VLSI systems with the CAMAD design aid (ZP), pp. 278–284.
DAC-1986-BruckKKR #algorithm #composition #concurrent #synthesis: Synthesis of concurrent modular controllers from algorithmic descriptions (RB, BK, TK, FJR), pp. 285–292.
DAC-1986-NaharSS #combinator #optimisation: Simulated annealing and combinatorial optimization (SN, SS, ES), pp. 293–299.
DAC-1986-Szepieniec #slicing: Integrated placement/routing in sliced layouts (AAS), pp. 300–307.
DAC-1986-JustKJ #layout #on the #problem #standard: On the relative placement and the transportation problem for standard-cell layout (KMJ, JMK, FMJ), pp. 308–313.
DAC-1986-Hartoog #analysis #layout #standard: Analysis of placement procedures for VLSI standard cell layout (MRH), pp. 314–319.
DAC-1986-Shahdad #overview: An overview of VHDL language and technology (MS), pp. 320–326.
DAC-1986-Eurich #design #tutorial: A tutorial introduction to the electronic design interchange format (JPE), pp. 327–333.
DAC-1986-Daehn #difference #fault: A unified treatment of PLA faults by Boolean differences (WD), pp. 334–338.
DAC-1986-LigthartAB #statistics #using: Design-for-testability of PLA’s using statistical cooling (MML, EHLA, FPMB), pp. 339–345.
DAC-1986-LadjadjMHM #array #testing #using: Use of the subscripted DALG in submodule testing with applications in cellular arrays (ML, JFM, DHH, WM), pp. 346–353.
DAC-1986-OhnoMYOKI #design #scalability: Principles of design automatioon system for very large scale computer design (YO, MM, NY, TO, TK, KI), pp. 354–359.
DAC-1986-MiyoshiOSOA #design #logic #scalability #simulation: An extensive logic simulation method of very large scale computer design (MM, YO, AS, NO, NA), pp. 360–365.
DAC-1986-TsuchiyaMITMY #design #logic #scalability: Establishment of higher level logic design for very large scale computer (YT, MM, YI, ET, TM, TY), pp. 366–371.
DAC-1986-Tryon #correlation #fault #self: Self-testing with correlated faults (DRT), pp. 374–377.
DAC-1986-Kruger #automation #design #generative #self #source code: Automatic generation of self-test programs — a new feature of the MIMOLA design system (GK), pp. 378–384.
DAC-1986-KuoF #array #configuration management #performance: Efficient spare allocation in reconfigurable arrays (SYK, WKF), pp. 385–390.
DAC-1986-ShinshaKSKI #identification #incremental #logic #synthesis: Incremental logic synthesis through gate logic structure identification (TS, TK, YS, JK, KI), pp. 391–397.
DAC-1986-ToyoshimaTMHHKT #analysis #design #effectiveness #scalability: An effective delay analysis system for a large scale computer design (RT, YT, KM, HH, MH, RK, KT), pp. 398–403.
DAC-1986-OgawaISTKYC #algorithm #optimisation #performance: Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.
DAC-1986-NaharS #performance: A time and space efficient net extractor (SN, SS), pp. 411–417.
DAC-1986-FreemanKLN #automation #layout #matrix #modelling: Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.
DAC-1986-BootehsazC #approach #independence #layout: A technology independent approach to hierarchical IC layout extraction (AB, RAC), pp. 425–431.
DAC-1986-SechenS #standard: TimberWolf3.2: a new standard cell placement and global routing package (CS, ALSV), pp. 432–439.
DAC-1986-HaugeY #design #named #physics: Vanguard: a chip physical design system (PSH, EJY), pp. 440–446.
DAC-1986-KrekelbergSSL #automation #compilation #layout #synthesis: Automated layout synthesis in the YASC silicon compiler (DEK, ES, GES, LSL), pp. 447–453.
DAC-1986-ParkP #named #pipes and filters #synthesis: Sehwa: a program for synthesis of pipelines (NP, ACP), pp. 454–460.
DAC-1986-ParkerPM #named #synthesis: MAHA: a program for datapath synthesis (ACP, JTP, MJM), pp. 461–466.
DAC-1986-KurdahiP #estimation #named: PLEST: a program for area estimation of VLSI integrated circuits (FJK, ACP), pp. 467–473.
DAC-1986-McFarland #behaviour #bottom-up #design #hardware #synthesis #using: Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions (MCM), pp. 474–480.
DAC-1986-LukTW #design: Hierarchial global wiring for custom chip design (WKL, DTT, CKW), pp. 481–489.
DAC-1986-Ng #industrial: An industrial world channel router for non-rectangular channels (CHN), pp. 490–494.
DAC-1986-BraunBDMMRS #multi #named: Chameleon: a new multi-layer channel router (DB, JLB, SD, HKTM, KM, FR, ALSV), pp. 495–502.
DAC-1986-OrailogluG #graph #representation: Flow graph representation (AO, DG), pp. 503–509.
DAC-1986-AudeK #adaptation #database #design: A design rule database system to support technology-adaptable applications (JSA, HJK), pp. 510–516.
DAC-1986-IvieL #named #simulation: STL — a high level language for simulation and test (JI, KWLL), pp. 517–523.
DAC-1986-Solworth #compilation #named: GENERIC: a silicon compiler support language (JAS), pp. 524–530.
DAC-1986-BirminghamJK #tutorial: Knowlege-based expert systems and their application (tutorial session (WPB, RJ, JK), pp. 531–539.
DAC-1986-WunderlichR #fault #modelling #on the: On fault modeling for dynamic MOS circuits (HJW, WR), pp. 540–546.
DAC-1986-PatelP #automation #effectiveness #generative #heuristic #metric: Effectiveness of heuristics measures for automatic test pattern generation (SJP, JHP), pp. 547–552.
DAC-1986-MaS #estimation #fault: Mixed-level fault coverage estimation (HKTM, ALSV), pp. 553–559.
DAC-1986-Maly #order #sequence #testing: Optimal order of the VLSI IC testing sequence (WM), pp. 560–566.
DAC-1986-KravitzR #multi: Multiprocessor-based placement by simulated annealing (SAK, RAR), pp. 567–573.
DAC-1986-WatanabeS #algorithm #hardware #implementation: A new routing algorithm and its hardware implementation (TW, YS), pp. 574–580.
DAC-1986-TakasakiSNIK #hardware #logic #simulation: HAL II: a mixed level hardware logic simulation system (ST, TS, NN, HI, NK), pp. 581–587.
DAC-1986-JacobNP #analysis #empirical #multi #performance: An empirical analysis of the performance of a multiprocessor-based circuit simulator (GKJ, ARN, DOP), pp. 588–593.
DAC-1986-SaitoSYK #array #logic #rule-based #synthesis: A rule-based logic circuit synthesis system for CMOS gate arrays (TS, HS, MY, NK), pp. 594–600.
DAC-1986-WatanabeA #design #named: Flute — a floorplanning agent for full custom VLSI design (HW, BDA), pp. 601–607.
DAC-1986-WatanabeMNH #generative #knowledge-based #logic: Knowledge-based optimal IIL generator from conventional logic circuit descriptions (TW, TM, TN, NH), pp. 608–614.
DAC-1986-DeJesusCW #layout #named #power management: PEARL: an expert system for power supply layout (EJD, JPC, CRW), pp. 615–621.
DAC-1986-PreasK #automation #overview: Automatic placement a review of current techniques (BP, PGK), pp. 622–629.
DAC-1986-DevadasN #array #named #synthesis: GENIE: a generalized array optimizer for VLSI synthesis (SD, ARN), pp. 631–637.
DAC-1986-Gerveshi #comparison #logic: Comparison of CMOS PLA and polycell representations of control logic (CMG), pp. 638–642.
DAC-1986-Coppola #heuristic #implementation: An implementation of a state assignment heuristic (AJC), pp. 643–649.
DAC-1986-ClarkeF #geometry #layout #named #recursion: Escher — a geometrical layout system for recursively defined circuits (EMC, YF), pp. 650–653.
DAC-1986-FrisonG #editing #layout #metaprogramming #named: MADMACS: a new VLSI layout macro editor (PF, EG), pp. 654–658.
DAC-1986-NgTR: A language for describing rectilinear Steiner tree configurations (APCN, CDT, PR), pp. 659–662.
DAC-1986-NandyR #design #representation: Dual quadtree representation for VLSI designs (SKN, LVR), pp. 663–666.
DAC-1986-LathropK: Precedent-based manipulation of VLSI structures (RHL, RSK), pp. 667–670.
DAC-1986-AdolphRS #design #representation: A frame based system for representing knowledge about VLSI design: a proposal (WSA, HKR, AS), pp. 671–676.
DAC-1986-Ghosh #approach #fault #functional #rule-based #simulation #verification: A rule-based approach to unifying functional and fault simulation and timing verification (SG), pp. 677–682.
DAC-1986-WallaceS #modelling #plugin #verification: Plug-in timing models for an abstract timing verifier (DEW, CHS), pp. 683–689.
DAC-1986-PincusD #reduction #using: Delay reduction using simulated annealing (JDP, AMD), pp. 690–695.
DAC-1986-NavedaCD #approach #multi: A new approach to multi-layer PCB routing with short vias (JFN, KCC, DHCD), pp. 696–701.
DAC-1986-ChangD #preprocessor #problem: A preprocessor for the via minimization problem (KCC, DHCD), pp. 702–707.
DAC-1986-EnbodyD: Near-optimal n-layer channel routing (RJE, DHCD), pp. 708–714.
DAC-1986-JerrayaVJC #compilation: Principles of the SYCO compiler (AAJ, PV, RJ, BC), pp. 715–721.
DAC-1986-MarshburnLBCLC #assembly #named: DATAPATH: a CMOS data path silicon assembler (TM, IL, RB, DC, GL, PC), pp. 722–729.
DAC-1986-SixCRM #generative: An intelligent module generator environment (PS, LJMC, JMR, HDM), pp. 730–735.
DAC-1986-PutatundaSMC #compilation #named: HAPPI: a chip compiler based on double-level-metal technology (RP, DS, SM, JC), pp. 736–743.
DAC-1986-Wolf #database #object-oriented: An object-oriented, procedural database for VLSI chip planning (WW), pp. 744–751.
DAC-1986-Gonzalez-SustaetaB #automation #concept #database #design #using: An automated database design tool using the ELKA conceptual model (JGS, APB), pp. 752–759.
DAC-1986-JullienLL #database #interface: A database interface for an integrated CAD system (CJ, AL, JL), pp. 760–767.
DAC-1986-Larsen #analysis #clustering #data type #synthesis: Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis (RPL), pp. 768–777.
DAC-1986-Canright #simulation: Simulating and controlling the effects of transmission line impedance mismatches (REC), pp. 778–785.
DAC-1986-KishidaSIIH #logic: A delay test system for high speed logic LSI’s (KK, FS, YI, SI, TH), pp. 786–790.
DAC-1986-TadaH #performance #scalability: Router system for printed wiring boards of very high-speed, very large-scale computers (TT, AH), pp. 791–797.
DAC-1986-KessenichJ: Global forced hierarchical router (JK, GJ), pp. 798–802.
DAC-1986-KawamuraUS: Hierarchical dynamic router (KK, MU, HS), pp. 803–809.
DAC-1986-BobbaS: A parameter-driven router (VSB, JWS), pp. 810–818.
DAC-1986-Lamey #design #prototype #verification: Early verification of prototype tooling for IC designs (PL), pp. 819–822.
DAC-1986-Xiong #algorithm: Algorithms for global routing (JGX), pp. 824–830.

Don ThomasProceedings of the 23rd Design Automation ConferenceDAC, 1986.

Contents (122 items)

Don Thomas
Proceedings of the 23rd Design Automation Conference
DAC, 1986.