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Travelled to:
1 × USA
Collaborated with:
D.A.Penry D.Fay D.Hodgdon G.Schelle D.I.August D.Connors
Talks about:
processor (1) structur (1) parallel (1) exploit (1) acceler (1) simul (1) multi (1) chip (1)

Person: Ryan Wells

DBLP DBLP: Wells:Ryan

Contributed to:

HPCA 20062006

Wrote 1 papers:

HPCA-2006-PenryFHWSAC #parallel #simulation
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors (DAP, DF, DH, RW, GS, DIA, DC), pp. 29–40.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.