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Travelled to:
1 × France
Collaborated with:
J.Figueras
Talks about:
variabl (1) circuit (1) weight (1) switch (1) combin (1) under (1) model (1) maxim (1) delay (1) activ (1)

Person: Salvador Manich

DBLP DBLP: Manich:Salvador

Contributed to:

ED&TC 19971997

Wrote 1 papers:

EDTC-1997-ManichF #process
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.