Travelled to:3 × Germany
5 × France
Collaborated with:E.I.Vatajelu R.Rodríguez-Montañés M.Renovell J.M.Portal Y.Zorian J.Rius S.Manich E.Isern A.Gomez R.Sanahuja L.Balado M.Indaco P.Prinetto C.Metra G.A.Mojoli S.Pastore D.Salvi G.R.Sechi
Talks about:test (7) circuit (4) base (4) sram (3) cmos (3) techniqu (2) sequenti (2) configur (2) analysi (2) robust (2)
Person: Joan Figueras
DBLP: Figueras:Joan
Contributed to:
20152012201120101999199819971994Wrote 12 papers:
- DATE-2015-VatajeluRIRPF #estimation #metric #robust
- Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.
- DATE-2012-VatajeluF #evaluation #parametricity #performance #reliability
- Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation (EIV, JF), pp. 1343–1348.
- DATE-2011-VatajeluF #analysis #in memory #memory management #robust
- Robustness analysis of 6T SRAMs in memory retention mode under PVT variations (EIV, JF), pp. 980–985.
- DATE-2010-GomezSBF
- Analog circuit test based on a digital signature (AG, RS, LB, JF), pp. 1641–1644.
- DATE-1999-RenovellPFZ #configuration management #interface #logic #testing
- Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
- DATE-1999-RiusF #energy #testing
- Exploring the Combination of IDDQ and iDDt Testing: Energy Testing (JR, JF), pp. 543–548.
- DATE-1998-MetraRMPPFZSS #novel #testing
- Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.
- DATE-1998-RenovellPFZ #approach #configuration management #logic
- RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
- DATE-1998-Rodriguez-MontanesF #estimation
- Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs (RRM, JF), pp. 490–494.
- EDTC-1997-ManichF #process
- Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.
- EDAC-1994-IsernF #fault
- Test of Bridging Faults in Scan-based Sequential Circuits (EI, JF), pp. 366–370.
- EDAC-1994-Rodriguez-MontanesF #analysis #fault #testing
- Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability (RRM, JF), pp. 356–360.