Proceedings of the Second European Design and Test Conference
ED&TC, 1997.

@proceedings{EDTC-1997,
	address       = "Paris, France",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the Second European Design and Test Conference}",
	year          = 1997,
}

Contents (114 items)

18 ×#testing
14 ×#design
14 ×#using
11 ×#generative
11 ×#multi
10 ×#performance
10 ×#synthesis
7 ×#analysis
6 ×#architecture
6 ×#fault

EDTC-1997-DasdanMG #analysis #constraints #debugging #embedded #named

RATAN: A tool for rate analysis and rate constraint debugging for embedded systems (AD, AM, RKG), pp. 2–6.

EDTC-1997-PandaDN #embedded #memory management #performance

Efficient utilization of scratch-pad memory in embedded processor applications (PRP, NDD, AN), pp. 7–11.

EDTC-1997-GirodiasC #constraints #correlation #interface #logic programming #using #verification

Interface timing verification with delay correlation using constraint logic programming (PG, EC), pp. 12–19.

EDTC-1997-HsiaoRP #generative #testing #traversal #using

Sequential circuit test generation using dynamic state traversal (MSH, EMR, JHP), pp. 22–28.

EDTC-1997-DargelasGB #multi #named

MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits (AD, CG, YB), pp. 29–36.

EDTC-1997-CornoPRR #sequence #testing

New static compaction techniques of test sequences for sequential circuits (FC, PP, MR, MSR), pp. 37–43.

EDTC-1997-BenabesKK #design

A methodology for designing continuous-time sigma-delta modulators (PB, MK, RK), pp. 46–50.

EDTC-1997-LuS

A CMOS low-voltage, high-gain op-amp (GNL, GS), pp. 51–55.

EDTC-1997-DonnayGSKLB #interface #synthesis

High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.

EDTC-1997-NouraniP #analysis #behaviour #using

Structural BIST insertion using behavioral test analysis (MN, CAP), pp. 64–68.

EDTC-1997-DufazaZ #generative #on the #pseudo #sequence #testing

On the generation of pseudo-deterministic two-patterns test sequence with LFSRs (CD, YZ), pp. 69–76.

EDTC-1997-KagarisT #automaton #generative #sequence #testing

Cellular automata for generating deterministic test sequences (DK, ST), pp. 77–81.

EDTC-1997-HertwigW #performance

Fast controllers for data dominated applications (AH, HJW), pp. 84–89.

EDTC-1997-IwamaHKS #benchmark #metric #random

Random benchmark circuits with controlled attributes (KI, KH, HK, SS), pp. 90–97.

EDTC-1997-CortadellaKKLY #composition #independence

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.

EDTC-1997-HofmannGSMMSKC #generative

Generation of the HDL-A-model of a micromembrane from its finite-element-description (KH, MG, NS, AM, SM, JS, JMK, BC), pp. 108–112.

EDTC-1997-WunscheCSW #design #using

Microsystem design using simulator coupling (SW, CC, PS, FW), pp. 113–118.

EDTC-1997-RomanowiczLLRABMP #hardware #modelling #simulation #transducer #using

Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language (BR, ML, PL, PR, HPA, AB, VM, FP), pp. 119–123.

EDTC-1997-SmeetsAEK #programmable #video

Delay management for programmable video signal processors (MLGS, EHLA, GE, EAdK), pp. 126–133.

EDTC-1997-LiW #multi #scheduling

Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors (YL, WW), pp. 134–139.

EDTC-1997-LeupersM #generative #modelling

Retargetable generation of code selectors from HDL processor models (RL, PM), pp. 140–144.

EDTC-1997-BhattacharyaDS #testing

An RTL methodology to enable low overhead combinational testing (SB, SD, BS), pp. 146–152.

EDTC-1997-GuLKP #analysis #testing

A controller testability analysis and enhancement technique (XG, EL, KK, ZP), pp. 153–157.

EDTC-1997-FlottesPR #behaviour #testing

Analyzing testability from behavioral to RT level (MLF, RP, BR), pp. 158–165.

EDTC-1997-HettDB #order #performance #synthesis

Fast and efficient construction of BDDs by reordering based synthesis (AH, RD, BB), pp. 168–175.

EDTC-1997-CabodiCLQ #synthesis #verification

Verification and synthesis of counters based on symbolic techniques (GC, PC, LL, SQ), pp. 176–181.

EDTC-1997-KropfR #model checking #using

Using MTBDDs for discrete timed symbolic model checking (TK, JR), pp. 182–187.

EDTC-1997-FradinMD #3d #analysis

Analysis of 3D conjugate heat transfers in electronics (JPF, LM, BD), pp. 190–194.

EDTC-1997-TangelderDK

Smart sensor system application: an integrated compass (RJWTT, GD, HGK), pp. 195–199.

EDTC-1997-LangDG #automation #design #modelling #parametricity #top-down

Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems (ML, DD, MG), pp. 200–204.

EDTC-1997-CmarV #architecture #parallel #scalability

Highly scalable parallel parametrizable architecture of the motion estimator (RC, SV), pp. 208–212.

EDTC-1997-RoyoML #design #encryption #implementation

Design and implementation of a coprocessor for cryptography applications (AR, JM, JCL), pp. 213–217.

EDTC-1997-RiescoDMCSJ #multi #network #on the

On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC (JR, JCD, LAM, JLC, CS, EJM), pp. 218–222.

EDTC-1997-Coudert #graph #optimisation #problem

Solving graph optimization problems with ZBDDs (OC), pp. 224–228.

EDTC-1997-SchollMHM #symmetry

Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries (CS, SM, GH, PM), pp. 229–234.

EDTC-1997-WahbaB #fault

Connection error location and correction in combinational circuits (AMW, DB), pp. 235–241.

EDTC-1997-Fishburn

Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.

EDTC-1997-KunduG #analysis

Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.

EDTC-1997-GeigenmullerM #3d #integration #multi

Cartesian multipole based numerical integration for 3D capacitance extraction (UG, NPvdM), pp. 256–259.

EDTC-1997-StopjakovaM #monitoring #testing

CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits (VS, HARM), pp. 266–270.

EDTC-1997-Sachdev #testing

Deep sub-micron IDDQ testing: issues and solutions (MS), pp. 271–278.

EDTC-1997-LaquaiRW #metric #performance #testing

A production-oriented measurement method for fast and exhaustive Iddq tests (BL, HR, HW), pp. 279–286.

EDTC-1997-JhaD #library

Library mapping for memories (PKJ, NDD), pp. 288–292.

EDTC-1997-MirandaKCM #architecture #generative #hardware #optimisation

Architectural exploration and optimization for counter based hardware address generation (MM, MK, FC, HDM), pp. 293–298.

EDTC-1997-XuK #physics #synthesis

RTL synthesis with physical and controller information (MX, FJK), pp. 299–303.

EDTC-1997-SeongK #clustering #design #layout

Two-way partitioning based on direction vector [layout design] (KSS, CMK), pp. 306–310.

EDTC-1997-LiuS #graph #heuristic #multi #performance #using

Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic (LCEL, CS), pp. 311–318.

EDTC-1997-TsengS #multi #standard #using

A gridless multi-layer router for standard cell circuits using CTM cells (HPT, CS), pp. 319–326.

EDTC-1997-ChakrabortyM #bound #functional #parallel #programmable #testing

A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs (KC, PM), pp. 330–334.

EDTC-1997-DuarteNBZ #design #implementation

Fault-secure shifter design: results and implementations (RdOD, MN, HB, YZ), pp. 335–341.

EDTC-1997-HuangW #array #design #performance

High-speed C-testable systolic array design for Galois-field inversion (CTH, CWW), pp. 342–346.

EDTC-1997-ArabiK #performance #testing #using

Efficient and accurate testing of analog-to-digital converters using oscillation-test method (KA, BK), pp. 348–352.

EDTC-1997-VriesZBR #self

Built-in self-test methodology for A/D converters (RdV, TZ, EMJGB, PPLR), pp. 353–358.

EDTC-1997-Lee #configuration management

Reconfigurable data converter as a building block for mixed-signal test (EKFL), pp. 359–363.

EDTC-1997-WalkerG #simulation

VHDL extensions for complex transmission line simulation (PW, SG), pp. 368–372.

EDTC-1997-ShojiHSKN #behaviour #simulation

Acceleration of behavioral simulation on simulation specific machines (MS, FH, SS, SK, HN), pp. 373–377.

EDTC-1997-WalkerG97a #distributed #independence #simulation

Exploiting temporal independence in distributed preemptive circuit simulation (PW, SG), pp. 378–382.

EDTC-1997-WalczowskiNWS #generative #layout #web

Analogue layout generation by World Wide Web server-based agents (LTW, DN, WAJW, KHS), pp. 384–388.

EDTC-1997-PrietoRQH #algorithm #optimisation

A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs (JAP, AR, JMQ, JLH), pp. 389–394.

EDTC-1997-Garcia-VargasGFR #algorithm #analysis #generative #scalability

An algorithm for numerical reference generation in symbolic analysis of large analog circuits (IGV, MG, FVF, ÁRV), pp. 395–399.

EDTC-1997-BoglioloBM #adaptation #behaviour #modelling

Adaptive least mean square behavioral power modeling (AB, LB, GDM), pp. 404–410.

EDTC-1997-GavrilovGRBJV #performance

Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.

EDTC-1997-SaxenaNH #approach #estimation #monte carlo

Monte-Carlo approach for power estimation in sequential circuits (VS, FNN, INH), pp. 416–420.

EDTC-1997-ChiusanoCPR #graph #hybrid #problem

Hybrid symbolic-explicit techniques for the graph coloring problem (SC, FC, PP, MSR), pp. 422–426.

EDTC-1997-EisenbieglerKB #approach #correctness #towards

A constructive approach towards correctness of synthesis-application within retiming (DE, RK, CB), pp. 427–431.

EDTC-1997-HendricxC #approach #verification

A symbolic core approach to the formal verification of integrated mixed-mode applications (SH, LJMC), pp. 432–436.

EDTC-1997-BolchiniSS #design #network #novel

A novel methodology for designing TSC networks based on the parity bit code (CB, FS, DS), pp. 440–444.

EDTC-1997-FavalliM #testing

Testing scheme for IC’s clocks (MF, CM), pp. 445–449.

EDTC-1997-PaschalisGGK #fault #self

A totally self-checking 1-out-of-3 code error indicator (AMP, NG, DG, PK), pp. 450–454.

EDTC-1997-GovindarajanV #algorithm #clustering #heuristic

Cone-based clustering heuristic for list-scheduling algorithms (SG, RV), pp. 456–462.

EDTC-1997-HerrmannE #synthesis

Register synthesis for speculative computation (DH, RE), pp. 463–467.

EDTC-1997-VerhaeghLAM #approach #multi #scheduling

Multidimensional periodic scheduling: a solution approach (WFJV, PERL, EHLA, JLvM), pp. 468–474.

EDTC-1997-ThoenSJGM #embedded #graph #multi #realtime #synthesis #thread

Multi-thread graph: a system model for real-time embedded software synthesis (FT, JVDS, GGdJ, GG, HDM), pp. 476–481.

EDTC-1997-GrotkerSM #data flow #modelling #named

PCC: a modeling technique for mixed control/data flow systems (TG, RS, HM), pp. 482–486.

EDTC-1997-Vahid #clustering #functional

Procedure cloning: a transformation for improved system-level functional partitioning (FV), pp. 487–492.

EDTC-1997-NarayananSKLB #fault

A fault diagnosis methodology for the UltraSPARCTM-I microprocessor (SN, RS, RPK, MEL, SBN), pp. 494–500.

EDTC-1997-SousaC

Improved diagnosis of realistic interconnect shorts (JTdS, PYKC), pp. 501–505.

EDTC-1997-PomeranzR #generative #on the #optimisation #search-based #testing

On improving genetic optimization based test generation (IP, SMR), pp. 506–511.

EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.

EDTC-1997-SurtiCT #automaton #design #encoding #power management #using

Low power FSM design using Huffman-style encoding (PS, LFC, AT), pp. 521–525.

EDTC-1997-ChoiH #estimation

Improving the accuracy of support-set finding method for power estimation of combinational circuits (HC, SHH), pp. 526–530.

EDTC-1997-GibsonA #concurrent #design #verification

Practical concurrent ASIC and system design and verification (IG, CA), pp. 532–536.

EDTC-1997-Schneider #abstraction #architecture #hardware #trade-off

A methodology for hardware architecture trade-off at different levels of abstraction (CS), pp. 537–541.

EDTC-1997-SchaumontVREB #multi #synthesis

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.

EDTC-1997-DrechslerHSHB #testing

Testability of 2-level AND/EXOR circuits (RD, HH, HS, JH, BB), pp. 548–553.

EDTC-1997-PomeranzR97a #finite #on the #state machine #testing

On the use of reset to increase the testability of interconnected finite-state machines (IP, SMR), pp. 554–559.

EDTC-1997-BensoPRRU #approach #fault #graph #low level

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (AB, PP, MR, MSR, RU), pp. 560–565.

EDTC-1997-RenovellAB

On-chip analog output response compaction (MR, FA, YB), pp. 568–572.

EDTC-1997-OlbrichGARC #estimation #quality

A new quality estimation methodology for mixed-signal and analogue ICs (TO, IAG, YEA, AMDR, JC), pp. 573–580.

EDTC-1997-KaalK #generative #metaprogramming #testing

Compact structural test generation for analog macros (VK, HGK), pp. 581–587.

EDTC-1997-CrenshawS #estimation

Accurate high level datapath power estimation (JEC, MS), pp. 590–596.

EDTC-1997-ManichF #process

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.

EDTC-1997-TurgisDPA #modelling

Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.

EDTC-1997-FauraHKCAI #integration #programmable

A new field programmable system-on-a-chip for mixed signal integration (JF, CH, BK, JC, MAA, JMI), p. 610.

EDTC-1997-LeijtenMTJ #architecture #data-driven #multi #named

PROPHID: a data-driven multi-processor architecture for high-performance DSP (JAJL, JLvM, AHT, JAGJ), p. 611.

EDTC-1997-LiemPJ #design #embedded #named

ReCode: the design and re-design of the instruction codes for embedded instruction-set processors (CL, PGP, AAJ), p. 612.

EDTC-1997-RowekampP #estimation #realtime #visual notation

A real-time smart sensor system for visual motion estimation (TR, LP), p. 613.

EDTC-1997-Gonzalez-TorresMH #set

Full custom chip set for high speed serial communications up to 2.48 Gbit/s (JGT, PAM, JMH), p. 614.

EDTC-1997-KarthikeyanN #architecture

An asynchronous architecture for digital signal processors (MRK, SKN), p. 615.

EDTC-1997-IhsD #synthesis

Test synthesis for DC test of switched-capacitors circuits (HI, CD), p. 616.

EDTC-1997-SzekelyPPRC #simulation

SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells (VS, AP, AP, MR, AC), p. 617.

EDTC-1997-ZarnikNM #design

Design of oscillation-based test structures for active RC filters (MSZ, FN, SM), p. 618.

EDTC-1997-BeckmannH #constraints #in memory #logic programming #memory management #synthesis #using

Using constraint logic programming in memory synthesis for general purpose computers (RB, JH), p. 619.

EDTC-1997-OzimekVT #array #implementation #performance #scheduling

Optimal scheduling for fast systolic array implementations (IO, RV, JFT), p. 620.

EDTC-1997-MignotteP #scheduling #using

Scheduling using mixed arithmetic: an ILP formulation (AM, OP), p. 621.

EDTC-1997-WalrathVB #analysis #partial evaluation #performance #using #verification

Performance verification using partial evaluation and interval analysis (JW, RV, WB), p. 622.

EDTC-1997-UrsuGZ #automaton #design #logic #specification #using #verification

Design and verification of the sequential systems automata using temporal logic specifications (AU, GG, SZ), p. 623.

EDTC-1997-WolfK #generative #independence

Application independent module generation in analog layouts (MW, UK), p. 624.

EDTC-1997-AbdullaRK #embedded #multi

A scheme for multiple on-chip signature checking for embedded SRAMs (MFA, CPR, AK), p. 625.

EDTC-1997-HigamiK #design #parallel

Design of partially parallel scan chain (YH, KK), p. 626.

EDTC-1997-GoorGYM #fault #memory management

March LA: a test for linked memory faults (AJvdG, GG, VNY, VGM), p. 627.

EDTC-1997-BlantonH #fault

The input pattern fault model and its application (RDB, JPH), p. 628.

EDTC-1997-SvajdaSM #monitoring

A monolithic off-chip IDDQ monitor (MS, BS, HARM), p. 629.

EDTC-1997-Kristof #architecture #bound #effectiveness #idea #self #testing

Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections (AK), p. 630.