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Travelled to:
2 × USA
Collaborated with:
C.Lin J.Lin C.Huang Y.Chiu
Talks about:
placement (2) consid (2) analog (2) constraint (1) capacitor (1) systemat (1) mismatch (1) centroid (1) boundari (1) perform (1)

Person: Soon-Jyh Chang

DBLP DBLP: Chang:Soon=Jyh

Contributed to:

DAC 20112011
DAC 20102010

Wrote 2 papers:

DAC-2011-LinLCHC #random
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits (CWL, JML, YCC, CPH, SJC), pp. 528–533.
DAC-2010-LinLHC #bound #constraints
Performance-driven analog placement considering boundary constraint (CWL, JML, CPH, SJC), pp. 292–297.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.