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Travelled to:
1 × France
4 × USA
Collaborated with:
Y.Chang C.Lin C.Huang S.Chang H.Chen Y.Chiu
Talks about:
tcg (3) represent (2) placement (2) floorplan (2) consid (2) analog (2) rectilinear (1) constraint (1) capacitor (1) arbitrari (1)

Person: Jai-Ming Lin

DBLP DBLP: Lin:Jai=Ming

Contributed to:

DAC 20112011
DAC 20102010
DAC 20022002
DATE 20022002
DAC 20012001

Wrote 5 papers:

DAC-2011-LinLCHC #random
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits (CWL, JML, YCC, CPH, SJC), pp. 528–533.
DAC-2010-LinLHC #bound #constraints
Performance-driven analog placement considering boundary constraint (CWL, JML, CPH, SJC), pp. 292–297.
DAC-2002-LinC #named #orthogonal
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans (JML, YWC), pp. 842–847.
DATE-2002-LinCC #using
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG (JML, HLC, YWC), pp. 69–75.
DAC-2001-LinC #graph #named #representation #transitive
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans (JML, YWC), pp. 764–769.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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