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Travelled to:
2 × USA
Collaborated with:
Talks about:
circuit (2) decomposit (1) synthesi (1) function (1) trigger (1) linear (1) glitch (1) reduc (1) power (1) negat (1)

Person: Tomasz S. Czajkowski

DBLP DBLP: Czajkowski:Tomasz_S=

Contributed to:

DAC 20082008
DAC 20072007

Wrote 2 papers:

DAC-2008-CzajkowskiB #composition #linear #logic #synthesis
Functionally linear decomposition and synthesis of logic circuits for FPGAs (TSC, SDB), pp. 18–23.
DAC-2007-CzajkowskiB #using
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (TSC, SDB), pp. 324–329.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.