BibSLEIGH corpus
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Used together with:
power (5)
reduct (3)
level (3)
fpga (3)
low (2)

Stem glitch$ (all stems)

10 papers:

PLDIPLDI-2015-LongfieldNMT #self #specification
Preventing glitches and short circuits in high-level self-timed chip specifications (SLJ, BN, RM, RT), pp. 270–279.
DATEDATE-2014-ZussaDTDMGCT #detection #fault #injection #performance
Efficiency of a glitch detector against electromagnetic fault injection (LZ, AD, KT, JMD, PM, LGS, JC, AT), pp. 1–6.
KDDKDD-2014-DasuLS #empirical
Empirical glitch explanations (TD, JML, DS), pp. 572–581.
DACDAC-2009-CromarLC #algorithm #reduction
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
DACDAC-2007-ChengCW #named #power management
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
DACDAC-2007-CzajkowskiB #using
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (TSC, SDB), pp. 324–329.
DATEDATE-2007-LinFYL #design #encryption #hardware
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware (KJL, SCF, SHY, CCL), pp. 1265–1270.
DACDAC-1999-HashimotoOT #design #power management #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DATEDATE-1999-BeniniMMMPS #power management
Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DACDAC-1996-RaghunathanDJ #analysis #reduction
Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.