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Travelled to:
1 × France
1 × Germany
Collaborated with:
F.Ferrandi A.Tumeo
Talks about:
reconfigur (1) bandwidth (1) synthesi (1) interfac (1) independ (1) schedul (1) control (1) analysi (1) system (1) regist (1)

Person: Vito Giovanni Castellana

DBLP DBLP: Castellana:Vito_Giovanni

Contributed to:

DATE 20142014
DATE 20132013

Wrote 2 papers:

DATE-2014-CastellanaTF #adaptation #configuration management #hybrid #interface #memory management
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems (VGC, AT, FF), pp. 1–4.
DATE-2013-CastellanaF #analysis #independence #liveness #scheduling #synthesis
Scheduling independent liveness analysis for register binding in high level synthesis (VGC, FF), pp. 1571–1574.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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