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Travelled to:
1 × France
2 × USA
Collaborated with:
C.J.Liu W.Wu G.Lu W.Wu W.Xu R.Krishnan L.He C.Kuo I.Tsai L.Chan
Talks about:
circuit (4) analog (2) dimension (1) techniqu (1) behavior (1) approach (1) statist (1) process (1) flexibl (1) coverag (1)

Person: Yen-Lung Chen

DBLP DBLP: Chen:Yen=Lung

Contributed to:

DAC 20142014
DATE 20132013
DAC 20102010

Wrote 3 papers:

DAC-2014-WuXKCH #named #simulation #statistics #towards
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage (WW, WX, RK, YLC, LH), p. 6.
DATE-2013-ChenWLL #automation #flexibility #process
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects (YLC, WRW, GRL, CNJL), pp. 1458–1461.
DAC-2010-KuoCTCL #approach #behaviour
Behavior-level yield enhancement approach for large-scaled analog circuits (CCK, YLC, ICT, LYC, CNJL), pp. 903–908.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.