BibSLEIGH — Lei

Travelled to:

13 × USA
2 × Germany
3 × France

Collaborated with:

H.Yu Y.Lin J.Xiong Y.Shi Y.Hu F.Gong K.H.Tam W.Liao C.Long L.Cheng F.Li R.Majumdar J.D.Z.Ma A.Saad J.Reed P.Hannigan E.Strauser B.Xiao C.Chu M.R.Stan K.M.Lepak I.Luwandi M.Jose Z.Cao B.Foo M.v.d.Schaar V.Shih T.Tuan P.Mesa L.J.Simonson W.Wu W.Xu R.Krishnan Y.Chen S.B.Luckenbill J.Lee P.Gupta C.J.Spanos K.Qian P.Wong J.L.Wong M.Potkonjak N.Chang S.Lin O.S.Nakagawa W.Xie D.Kim J.Ren J.Cong A.B.Kahng D.Noice N.Shirali S.H.Yen S.Liu G.Chen T.T.Jing T.Zhang R.Dutta X.Hong

Talks about:

reduct (9) power (9) fpga (6) analysi (5) dual (5) base (5) vdd (5) circuit (4) variat (4) consid (4)

Person: Lei He

DBLP: He:Lei

Contributed to:

2014

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1997

Wrote 34 papers:

DAC-2014-WuXKCH #named #simulation #statistics #towards: REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage (WW, WX, RK, YLC, LH), p. 6.
DAC-2011-GongYH #analysis #monte carlo #orthogonal #performance #probability: Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials (FG, HY, LH), pp. 298–303.
DAC-2010-GongYSKRH #constraints #estimation #named #parametricity #performance: QuickYield: an efficient global-search based parametric yield estimation with performance constraints (FG, HY, YS, DK, JR, LH), pp. 392–397.
DAC-2010-JoseHMH #robust: Rewiring for robustness (MJ, YH, RM, LH), pp. 469–474.
DAC-2010-XiaoSH #algorithm: A universal state-of-charge algorithm for batteries (BX, YS, LH), pp. 687–692.
DATE-2010-LuckenbillLHMH #algorithm #analysis #fault #logic #named #reliability: RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications (SBL, JYL, YH, RM, LH), pp. 783–788.
DAC-2009-ChengGSQH #modelling #variability: Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability (LC, PG, CJS, KQ, LH), pp. 104–109.
DAC-2009-GongYH #incremental #named #parallel #probability #process: PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation (FG, HY, LH), pp. 764–769.
DAC-2008-CaoFHS #algorithm #multi #scalability: Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications (ZC, BF, LH, MvdS), pp. 179–184.
DAC-2008-HuSMH #multi #reduction: FPGA area reduction by multi-output function based sequential resynthesis (YH, VS, RM, LH), pp. 24–29.
DAC-2008-LiuCJHZDH: Topological routing to maximize routability for package substrate (SL, GC, TTJ, LH, TZ, RD, XH), pp. 566–569.
SIGITE-2008-HeSRHS #education #interactive #network #student #web: Information technology education for k-12 students and teachers: from sensor network to comprehensive and customized web interaction (LH, AS, JR, PH, ES), pp. 65–70.
SIGITE-2008-SaadHRSH #education #named #student: Ossabest: a comprehensive itest project for middle and high school teachers and students (AS, LH, JR, ES, PH), pp. 71–76.
DAC-2007-ChengXH #analysis #statistics: Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources (LC, JX, LH), pp. 250–255.
DAC-2007-YuCH #co-evolution #design: Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design (HY, CC, LH), pp. 618–621.
DATE-2007-LinH #interactive #reduction #statistics: Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
DAC-2006-HuLHT #reduction: Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
DAC-2006-ShiMYH #simulation: Circuit simulation based obstacle-aware Steiner routing (YS, PM, HY, LH), pp. 385–388.
DAC-2006-YuSH #analysis #grid #order #performance #power management #reduction: Fast analysis of structured power grid by triangularization based structure preserving model order reduction (HY, YS, LH), pp. 205–210.
DAC-2005-ChengWLLH #architecture #reduction: Device and architecture co-optimization for FPGA power reduction (LC, PW, FL, YL, LH), pp. 915–920.
DAC-2005-LinH #performance #reduction: Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DAC-2005-TamH: Power optimal dual-Vdd buffered tree considering buffer stations and blockages (KHT, LH), pp. 497–502.
DATE-2005-WongLLHP #realtime #scheduling: Scheduling of Soft Real-Time Systems for Context-Aware Applications (JLW, WL, FL, LH, MP), pp. 318–323.
DATE-2005-XiongTH #process: Buffer Insertion Considering Process Variation (JX, KHT, LH), pp. 970–975.
DAC-2004-HeLS #reduction: System level leakage reduction considering the interdependence of temperature and leakage (LH, WL, MRS), pp. 12–17.
DAC-2004-LiLH #configuration management #reduction #using: FPGA power reduction using configurable dual-Vdd (FL, YL, LH), pp. 735–740.
DAC-2004-LongSLH #optimisation #pipes and filters: Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects (CL, LJS, WL, LH), pp. 640–645.
DATE-v2-2004-XiongH #multi: Full-Chip Multilevel Routing for Power and Signal Integrity (JX, LH), pp. 1116–1123.
DAC-2003-LongH #distributed #network #reduction: Distributed sleep transistor network for power reduction (CL, LH), pp. 181–186.
DAC-2003-YuH: Vector potential equivalent circuit based on PEEC inversion (HY, LH), pp. 718–723.
DAC-2002-MaH #constraints #towards: Towards global routing with RLC crosstalk constraints (JDZM, LH), pp. 669–672.
DAC-2001-LepakLH #constraints: Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint (KML, IL, LH), pp. 199–202.
DATE-2000-ChangLNXH #modelling #performance: Clocktree RLC Extraction with Efficient Inductance Modeling (NC, SL, OSN, WX, LH), pp. 522–526.
DAC-1997-CongHKNSY #2d #analysis: Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology (JC, LH, ABK, DN, NS, SHCY), pp. 627–632.