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Travelled to:
2 × Germany
Collaborated with:
F.Gerfers N.Lotze J.Göppert
Talks about:
time (2) low (2) threshold (1) strategi (1) convert (1) continu (1) circuit (1) voltag (1) design (1) sigma (1)

Person: Yiannos Manoli

DBLP DBLP: Manoli:Yiannos

Contributed to:

DATE 20102010
DATE 20012001

Wrote 2 papers:

DATE-2010-LotzeGM #modelling
Timing modeling for digital sub-threshold circuits (NL, JG, YM), pp. 299–302.
DATE-2001-GerfersM #design #power management
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters (FG, YM), pp. 361–369.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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