19 papers:
DATE-2013-HuangMSBP #effectiveness #performance- A fast and Effective DFT for test and diagnosis of power switches in SoCs (XH, JM, RAS, SB, DKP), pp. 1089–1092.
- DATE-2011-BalasubramanianSMNDKMPPVT #low cost #power management #robust
- Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system (LB, PS, RKM, PN, RKD, ADK, SM, SP, HP, RCV, ST), pp. 551–554.
- DATE-2011-KumarRPB #3d #clustering #testing
- Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing (AK, SMR, IP, BB), pp. 1424–1429.
DAC-2007-IwataYF- A DFT Method for Time Expansion Model at Register Transfer Level (HI, TY, HF), pp. 682–687.
- DAC-2006-Al-Yamani
- DFT for controlled-impedance I/O buffers (AAAY), pp. 405–410.
- DAC-2005-TopalogluO #approach #process
- A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs (ROT, AO), pp. 851–856.
- DATE-2003-NummerS #pipes and filters #testing
- DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers (MN, MS), pp. 10212–10217.
- DAC-2002-AbramoviciYR #low cost
- Low-cost sequential ATPG with clock-control DFT (MA, XY, EMR), pp. 243–248.
- DAC-2001-Dervisoglu #architecture #data access
- A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers (BID), pp. 53–58.
- DAC-2001-LaiC #testing
- Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
- DATE-2001-WahlAMR #modelling #optimisation
- From DFT to systems test — a model based cost optimization tool (MGW, APA, CM, MR), pp. 302–306.
CIKM-2000-WuAA00a #comparison #database #similarity- A Comparison of DFT and DWT based Similarity Search in Time-Series Databases (YLW, DA, AEA), pp. 488–495.
- DATE-1998-RenovellAB #implementation #multi
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
- CIKM-1998-SaracEA #estimation
- Iterated DFT Based Techniques for Join Size Estimation (KS, ÖE, AEA), pp. 348–355.
- DAC-1997-ChangLMAC #approach #synthesis
- A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
- DAC-1994-FangG #low cost #testing
- Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.
- DAC-1994-ParulkarBN #representation
- Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
- EDAC-1994-McGowenF #case study #detection
- A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT (RM, FJF), pp. 371–375.
- DAC-1983-Bhavsar #algorithm #calculus #design
- Design For Test Calculus: An algorithm for DFT rules checking (DKB), pp. 300–307.
