10 papers:
DAC-2015-JangKGY0 #design- Bandwidth-efficient on-chip interconnect designs for GPGPUs (HJ, JK, PG, KHY, EJK), p. 6.
- DAC-2015-LiCSHLWY #hybrid #power management
- A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.
DATE-2015-TanLF #memory management #reliability #using- Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory (JT, ZL, XF), pp. 369–374.
- DAC-2014-ChenWLXY #optimisation #runtime
- Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs (XC, YW, YL, YX, HY), p. 6.
- DATE-2014-Bautista-GomezCCDFGPRR #how #named #reliability
- GPGPUs: How to combine high computational power with high reliability (LABG, FC, LC, ND, BF, SG, KP, PR, MSR), pp. 1–9.
- DATE-2014-RahimiBG #energy #fault
- Temporal memoization for energy-efficient timing error recovery in GPGPUs (AR, LB, RKG), pp. 1–6.
- DAC-2013-NathAR #concurrent #scheduling #thread
- Temperature aware thread block scheduling in GPGPUs (RN, RZA, TSR), p. 6.
HPCA-2013-Abdel-MajeedA #performance- Warped register file: A power efficient register file for GPGPUs (MAM, MA), pp. 412–423.
PPoPP-2012-FengGB #parallel- Speculative parallelization on GPGPUs (MF, RG, LNB), pp. 293–294.
- DATE-2009-ChatterjeeDB #named #simulation
- GCS: High-performance gate-level simulation with GPGPUs (DC, AD, VB), pp. 1332–1337.
