BibSLEIGH corpus
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Used together with:
high (3)
design (3)
logic (2)
system (2)
scale (2)

Stem lsis$ (all stems)

8 papers:

DACDAC-2006-NakamuraTOTY #design #scalability
Budgeting-free hierarchical design method for large scale and high-performance LSIs (YN, MT, TO, ST, KY), pp. 955–958.
HPCAHPCA-1999-InoueKM #logic #memory management
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (KI, KK, KM), pp. 218–222.
DACDAC-1997-MurofushiIMM #layout #power management
Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
DACDAC-1996-EdamatsuIH #design #video
Design Methodologies for consumer-use video signal processing LSIs (HE, SI, KH), pp. 497–502.
DACDAC-1991-OgawaIMIST #constraints #design
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design (YO, TI, YM, TI, YS, RT), pp. 253–258.
DACDAC-1986-OgawaISTKYC #algorithm #optimisation #performance
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.
DACDAC-1981-GoshimaOKMTO #logic #scalability
Diagnostic system for large scale logic cards and LSIs (SG, YO, TK, TM, YT, YO), pp. 256–259.
DACDAC-1974-KozawaHISS #automation #generative #layout
Advanced LILAC — an Automated Layout Generation system for MOS/LSIs (TK, HH, TI, JS, SS), pp. 26–46.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.