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Used together with:
simul (1)
eda (1)
calibr (1)
effici (1)
circuit (1)

Stem pll$ (all stems)

4 papers:

DATEDATE-2008-BinkleyGGR #design
From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DACDAC-2003-ManeatisKMMS #generative #multi #self
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (JGM, JK, IM, JM, MS), pp. 688–690.
DATEDATE-2003-MounirMF #automation #behaviour #performance #verification
Automatic Behavioural Model Calibration for Efficient PLL System Verification (AM, AM, MF), pp. 20280–20285.
DACDAC-2002-Perrott #behaviour #performance #simulation
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits (MHP), pp. 498–503.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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