BibSLEIGH — Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
DAC, 2003.

DAC 2003

@inproceedings{DAC-2003-ManeatisKMMS,
	author        = "John G. Maneatis and Jaeha Kim and Iain McClatchie and Jay Maxey and Manjusha Shankaradas",
	booktitle     = "{Proceedings of the 40th Design Automation Conference}",
	doi           = "10.1145/775832.776006",
	isbn          = "1-58113-688-9",
	pages         = "688--690",
	publisher     = "{ACM}",
	title         = "{Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL}",
	year          = 2003,
}

John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha ShankaradasSelf-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLLDAC, 2003.

Tags:

John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
DAC, 2003.