BibSLEIGH corpus
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BibSLEIGH bundles
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Used together with:
design (10)
challeng (10)
tool (6)
comput (3)
human (3)

Stem eda$ (all stems)

48 papers:

DACDAC-2015-WenWHLHLC #framework #hybrid #scalability
An EDA framework for large scale hybrid neuromorphic computing systems (WW, CRW, XH, BL, TYH, XL, YC), p. 6.
CASECASE-2014-HaoLGC #effectiveness #flexibility #markov #network #nondeterminism #problem #scheduling
An effective Markov network based EDA for flexible job shop scheduling problems under uncertainty (XCH, LL, MG, CFC), pp. 131–136.
DACDAC-2014-Rutenbar #automation #design #education
The First EDA MOOC: Teaching Design Automation to Planet Earth (RAR), p. 6.
DACDAC-2014-ShafiqueGHM #challenge #reliability #variability
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives (MS, SG, JH, DM), p. 6.
DACDAC-2014-WangA #constraints #data mining #mining
Data Mining In EDA — Basic Principles, Promises, and Constraints (LCW, MSA), p. 6.
DATEDATE-2014-Jin #evaluation #proving #security #tool support #trust
EDA tools trust evaluation through security property proofs (YJ), pp. 1–4.
An EDA-friendly protection scheme against side-channel attacks (AGB, NV, FR, DN, PB, PI), pp. 410–415.
DATEDATE-2013-BertaccoCBFVKP #on the
On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
DATEDATE-2013-GrimmMP #challenge #power management
Ultra-low power: an EDA challenge (CG, JM, XP), p. 483.
Humans for EDA and EDA for humans (VB), pp. 729–733.
DACDAC-2012-KoushanfarFMBSSP #question
Can EDA combat the rise of electronic counterfeiting? (FK, SF, CM, WB, MS, PS, MP), pp. 133–138.
DACDAC-2012-KoushanfarSS #challenge
EDA for secure and dependable cybercars: challenges and opportunities (FK, ARS, HS), pp. 220–228.
DATEDATE-2012-Graeb #challenge
ITRS 2011 Analog EDA Challenges and Approaches (HG), pp. 1150–1155.
DATEDATE-2012-MarinissenVGHRMB #detection #process
EDA solutions to new-defect detection in advanced process technologies (EJM, GV, SKG, FH, JR, NM, SB), pp. 123–128.
DATEDATE-2011-SommerKHSS #automation #design #generative #network
A new method for automated generation of compensation networks — The EDA Designer Finger (RS, DK, EH, ES, CS), pp. 1666–1672.
DACDAC-2010-KeshavaHP #challenge #how #validation
Post-silicon validation challenges: how EDA and academia can help (JK, NH, CP), pp. 3–7.
DACDAC-2010-PuriJJJRRS #challenge
EDA challenges and options: investing for the future (RP, WHJ, RJ, AJ, JMR, WCR, LS), pp. 1–2.
Human computing for EDA (AD, VB), pp. 621–622.
DACDAC-2009-HaritanKJERRG #question
EDA in flux: should I stay or should I go? (EH, AK, TJ, JE, JMR, RR, NG), pp. 91–92.
The day Sherlock Holmes decided to do EDA (AGV, SS), pp. 631–634.
DACDAC-2008-CatanzaroKS #research
Parallelizing CAD: a timely research agenda for EDA (BCC, KK, BYS), pp. 12–17.
DACDAC-2008-SapatnekarHKDKMPS #manycore
Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
DACDAC-2008-YagiRKHTMSDM #question
ESL hand-off: fact or EDA fiction? (HY, WR, TK, EH, HT, MM, GS, ND, GM), pp. 310–312.
DATEDATE-2008-BinkleyGGR #design
From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DACDAC-2007-BacchiniSCKGHY #roadmap
Megatrends and EDA 2017 (FB, GS, JAC, KK, AJdG, FCH, KY), pp. 21–22.
DACDAC-2007-KillpackKC #feedback #metric
Silicon Speedpath Measurement and Feedback into EDA flows (KK, CVK, EC), pp. 390–395.
DACDAC-2006-SheahanFWMM #challenge #design
4.25 Gb/s laser driver: design challenges and EDA tool limitations (BS, JWF, JW, KM, BM), pp. 863–866.
DATEDATE-2006-MaciiPFADZ #design #matter #power management #question #tool support
Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATEDATE-2006-Rhines #design
Sociology of design and EDA (WCR), p. 2.
DATEDATE-2006-Vries #challenge #convergence
EDA challenges in the converging application world (RPdV), p. 1.
DACDAC-2004-DahlbergKBGR #named
EDA: this is serious business (RD, KK, RB, AJdG, WCR), p. 1.
Were the good old days all that good?: EDA then and now (SR, WHJJ, JAD, DG, POP, HDM, CH, JS), p. 543.
Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
DACDAC-2003-Spirakis #challenge #design #question
Leading-edge and future design challenges — is the classical EDA ready? (GS), p. 416.
Wall street evaluates EDA (MG, RG, LL, VS, JV), p. 1.
DACDAC-2002-RabaeyKBCSLH #question #what
What’s the next EDA driver? (JMR, JK, DB, RC, DS, LL, RH), p. 652.
DACDAC-2002-Sotiriou #implementation #using
Implementing asynchronous circuits using a conventional EDA tool-flow (CPS), pp. 415–418.
DATEDATE-2002-PilarskiH #satisfiability
Speeding up SAT for EDA (SP, GH), p. 1081.
DATEDATE-2002-X #question #tool support
EDA Tools for RF: Myth or Reality?, pp. 292–293.
DATEDATE-2001-GielenSCMR #challenge #design
Design challenges and emerging EDA solutions in mixed-signal IC design (GGEG, BS, HC, PM, JR), pp. 694–695.
DACDAC-1999-KahngP #design
Subwavelength Lithography and Its Potential Impact on Design and EDA (ABK, YCP), pp. 799–804.
DACDAC-1996-HutchinsH #how #perl #tool support
How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together (RCH, SH), pp. 409–414.
DACDAC-1994-Fernandez #industrial
Intellectual Property Protection in the EDA Industry (DSF), pp. 161–163.
DACDAC-1994-Murphy #standard
Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards (SM), pp. 131–134.
Management Issues in Eda (AMP), pp. 41–47.
DATEEDAC-1994-Vitsyn #process #standard
The Russian EDA Standards Activities (NMV), p. 654.
The State of EDA in Russian Universities (VMM), pp. 716–719.
Linking TCAD to EDA — Benefits and Issues (GRC, WCDJ, DSB, ASW, ARN, RWD), pp. 573–578.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.