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Used together with:
system (7)
manufactur (5)
synthesi (5)
petri (4)
net (4)

Stem supervisor$ (all stems)

12 papers:

CASECASE-2015-AcarS #design #fault
Discrete event supervisor design and application for manufacturing systems with arbitrary faults and repairs (ANA, KWS), pp. 825–830.
CASECASE-2015-ChengHL #automation #petri net #robust #synthesis #using
Robust supervisor synthesis for automated manufacturing systems using Petri nets (YC, HH, YL), pp. 1029–1035.
SACSAC-2015-Messaoud #collaboration #named
Dynamic: a collaborative filtering strategy for assigning examination’s rooms to supervisors (MBM), pp. 264–266.
CASECASE-2014-HuCLY #approach #automation #comparative #petri net #using
A comparative approach to supervisor simplification in automated manufacturing systems using Petri nets (HH, CC, YL, YY), pp. 619–625.
CASECASE-2014-ZhaoUH #divide and conquer #flexibility #synthesis
A divide-and-conquer method for the synthesis of non-blocking supervisors for flexible manufacturing systems (MZ, MU, YH), pp. 455–460.
CASECASE-2013-HuZL #automation #performance #petri net #synthesis #using
Supervisor synthesis and performance improvement for automated manufacturing systems by using Petri nets (HH, MZ, YL), pp. 1139–1144.
CASECASE-2013-IordacheWZA #design #performance #petri net #specification
Efficient design of Petri-net supervisors with disjunctive specifications (MVI, PW, FZ, PJA), pp. 936–941.
DATEDATE-2013-KloosM #synthesis
Supervisor synthesis for controller upgrades (JK, RM), pp. 1105–1110.
CASECASE-2012-MohajeraniMF #composition #synthesis
Transition removal for compositional supervisor synthesis (SM, RM, MF), pp. 694–699.
CASECASE-2010-NazeemR #approach #design #resource management
A practical approach to the design of maximally permissive liveness-enforcing supervisors for complex resource allocation systems (AN, SR), pp. 451–458.
SEKESEKE-2002-Micucci #architecture #industrial #knowledge-based #monitoring
Exploiting the kaleidoscope architecture in an industrial environmental monitoring system with heterogeneous devices and a knowledge-based supervisor (DM), pp. 685–688.
ISSTATAV-1989-RosenblumL #correctness #specification #testing
Testing the Correctness of Tasking Supervisors with TSL Specifications (DSR, DCL), pp. 187–196.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.