BibSLEIGH corpus
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Used together with:
cmos (2)
circuit (2)
size (1)
high (1)
transistor (1)

Stem taper$ (all stems)

2 papers:

DATEDATE-2002-DingM #performance
Optimal Transistor Tapering for High-Speed CMOS Circuits (LD, PM), pp. 708–713.
CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.