Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
CMOS Combinational Circuit Sizing by Stage-wise Tapering
DATE, 1998.
@inproceedings{DATE-1998-PullelaPDV,
author = "Satyamurthy Pullela and Rajendran Panda and Abhijit Dharchoudhury and Gopal Vija",
booktitle = "{Proceedings of the Third Conference on Design, Automation and Test in Europe}",
doi = "10.1109/DATE.1998.656001",
pages = "985--986",
publisher = "{IEEE Computer Society}",
title = "{CMOS Combinational Circuit Sizing by Stage-wise Tapering}",
year = 1998,
}