Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
DAC, 1999.
@inproceedings{DAC-1999-HashimotoOT,
author = "Masanori Hashimoto and Hidetoshi Onodera and Keikichi Tamaru",
booktitle = "{Proceedings of the 36th Design Automation Conference}",
doi = "10.1145/309847.309977",
pages = "446--451",
publisher = "{ACM Press}",
title = "{A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design}",
year = 1999,
}