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Travelled to:
1 × USA
Collaborated with:
H.Onodera K.Tamaru
Talks about:
techniqu (1) practic (1) reduct (1) glitch (1) design (1) consid (1) resiz (1) power (1) gate (1) low (1)

Person: Masanori Hashimoto

DBLP DBLP: Hashimoto:Masanori

Contributed to:

DAC 19991999

Wrote 1 papers:

DAC-1999-HashimotoOT #design #power management #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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