10 papers:
PLDI-2015-LongfieldNMT #self #specification- Preventing glitches and short circuits in high-level self-timed chip specifications (SLJ, BN, RM, RT), pp. 270–279.
DATE-2014-ZussaDTDMGCT #detection #fault #injection #performance- Efficiency of a glitch detector against electromagnetic fault injection (LZ, AD, KT, JMD, PM, LGS, JC, AT), pp. 1–6.
KDD-2014-DasuLS #empirical- Empirical glitch explanations (TD, JML, DS), pp. 572–581.
DAC-2009-CromarLC #algorithm #reduction- FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
- DAC-2007-ChengCW #named #power management
- GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
- DAC-2007-CzajkowskiB #using
- Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (TSC, SDB), pp. 324–329.
- DATE-2007-LinFYL #design #encryption #hardware
- Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware (KJL, SCF, SHY, CCL), pp. 1265–1270.
- DAC-1999-HashimotoOT #design #power management #reduction
- A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
- DATE-1999-BeniniMMMPS #power management
- Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
- DAC-1996-RaghunathanDJ #analysis #reduction
- Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.
