Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter

Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
DAC, 2009.

DAC 2009
DBLP
Scholar
DOI
Full names Links ISxN
@inproceedings{DAC-2009-WangCSC,
	author        = "Renshen Wang and Nan-Chi Chou and Bill Salefski and Chung-Kuan Cheng",
	booktitle     = "{Proceedings of the 46th Design Automation Conference}",
	doi           = "10.1145/1629911.1629958",
	isbn          = "978-1-60558-497-3",
	pages         = "166--171",
	publisher     = "{ACM}",
	title         = "{Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications}",
	year          = 2009,
}

Tags:



Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.