Naresh Maheshwari, Sachin S. Sapatnekar
Efficient Minarea Retiming of Large Level-Clocked Circuits
DATE, 1998.
@inproceedings{DATE-1998-MaheshwariS,
author = "Naresh Maheshwari and Sachin S. Sapatnekar",
booktitle = "{Proceedings of the Third Conference on Design, Automation and Test in Europe}",
doi = "10.1109/DATE.1998.655956",
pages = "840--845",
publisher = "{IEEE Computer Society}",
title = "{Efficient Minarea Retiming of Large Level-Clocked Circuits}",
year = 1998,
}











