Stem retim$ (all stems)

49 papers:

DATE-2014-ZhuGBS #data flow #graph #scheduling

Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming (XYZ, MG, TB, SS), pp. 1–6.

DAC-2013-RamasubramanianVPR #design #energy #named

Relax-and-retime: a methodology for energy-efficient recovery based design (SGR, SV, AP, AR), p. 6.

DATE-2013-LuZ #constraints #fault

Retiming for Soft Error Minimization Under Error-Latching Window Constraints (YL, HZ), pp. 1008–1013.

DAC-2012-CheC #embedded #manycore

Unrolling and retiming of stream applications onto embedded multicore processors (WC, KSC), pp. 1272–1277.

DAC-2011-CheC #compilation #embedded #manycore #memory management #source code

Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming (WC, KSC), pp. 122–127.

DATE-2010-Zhu #algorithm #multi #realtime

Retiming multi-rate DSP algorithms to meet real-time requirement (XYZ), pp. 1785–1790.

DAC-2009-BufistovCOJK #evaluation

Retiming and recycling for elastic systems with early evaluation (DB, JC, MGO, JJ, MK), pp. 288–291.

DAC-2009-KrishnaswamyMH #testing

Improving testability and soft-error resilience through retiming (SK, ILM, JPH), pp. 508–513.

DAC-2008-HurstMB #constraints #scalability

Scalable min-register retiming under timing and initializability constraints (APH, AM, RKB), pp. 534–539.

DAC-2008-Moon #composition #optimisation #verification

Compositional verification of retiming and sequential optimizations (IHM), pp. 131–136.

DAC-2008-WangZ #algorithm #incremental #performance

An efficient incremental algorithm for min-area retiming (JW, HZ), pp. 528–533.

DAC-2006-HuLHT #reduction

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.

DAC-2006-LinZ #algorithm #constraints #performance

An efficient retiming algorithm under setup and hold constraints (CL, HZ), pp. 945–950.

DATE-2006-SovianiTE #composition #optimisation

Optimizing sequential cycles through Shannon decomposition and retiming (CS, OT, SAE), pp. 1085–1090.

DAC-2005-SinghMB #incremental #physics #synthesis

Incremental retiming for FPGA physical synthesis (DPS, VM, SDB), pp. 433–438.

TACAS-2005-Jiang #invariant #on the

On Some Transformation Invariants Under Retiming and Resynthesis (JHRJ), pp. 413–428.

CIAA-2005-Bartha #equivalence

Strong Retiming Equivalence of Synchronous Schemes (MB), pp. 66–77.

DATE-v2-2004-LinZ #fixpoint

Wire Retiming for System-on-Chip by Fixpoint Computation (CL, HZ), pp. 1092–1097.

DAC-2003-CongY #multi

Multilevel global placement with retiming (JC, XY), pp. 208–213.

DATE-2003-LuK

Interconnect Planning with Local Area Constrained Retiming (RL, CKK), pp. 10442–10447.

DATE-2003-SeidlEJ #using

Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (US, KE, FMJ), pp. 10770–10777.

CAV-2001-KuehlmannB #using #verification

Transformation-Based Verification Using Generalized Retiming (AK, JB), pp. 104–117.

DAC-2000-CabodiQS #optimisation #verification

Optimizing sequential verification by retiming transformations (GC, SQ, FS), pp. 601–606.

DAC-2000-CongLW #clustering #multi #performance

Performance driven multi-level and multiway partitioning with retiming (JC, SKL, CW), pp. 274–279.

DAC-2000-YuKW #representation

The use of carry-save representation in joint module selection and retiming (ZY, KYK, ANWJ), pp. 768–773.

DAC-1999-CongLW #clustering #optimisation #performance

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (JC, HL, CW), pp. 460–465.

DAC-1999-EcklMZL #approach #multi

A Practical Approach to Multiple-Class Retiming (KE, JCM, PZ, CL), pp. 237–242.

DAC-1999-LiuPF #performance #scheduling

Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.

DAC-1999-Pan #integration

Performance-Driven Integration of Retiming and Resynthesis (PP), pp. 243–246.

DAC-1999-TabbaraBN #constraints #trade-off

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (AT, RKB, ARN), pp. 725–730.

DATE-1999-EcklL #multi

Retiming Sequential Circuits with Multiple Register Classes (KE, CL), p. 650–?.

DATE-1999-KallaC #equivalence #performance

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence (PK, MJC), pp. 638–642.

DAC-1998-CongW #performance

Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (JC, CW), pp. 330–335.

DATE-1998-MaheshwariS #performance #scalability

Efficient Minarea Retiming of Large Level-Clocked Circuits (NM, SSS), pp. 840–845.

DAC-1997-CongW #pipes and filters #synthesis

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.

DAC-1997-MaheshwariS #algorithm

An Improved Algorithm for Minimum-Area Retiming (NM, SSS), pp. 2–7.

EDTC-1997-EisenbieglerKB #approach #correctness #towards

A constructive approach towards correctness of synthesis-application within retiming (DE, RK, CB), pp. 427–431.

PPoPP-1997-Prasanna #compilation #parallel

Compilation of Parallel Multimedia Computations — Extending Retiming Theory and Amdahl’s Law (GNSP), pp. 180–192.

DAC-1996-HassounE #architecture #pipes and filters

Architectural Retiming: Pipelining Latency-Constrained Circuts (SH, CE), pp. 708–713.

DAC-1996-LiouLC #performance #pipes and filters #pseudo #testing

Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming (HYL, TTYL, CKC), pp. 274–279.

DAC-1995-DeCastelo-Vide-e-SouzaPP #algorithm #approach #architecture #optimisation #throughput #using

Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming (YGDVeS, MP, ACP), pp. 113–118.

DAC-1995-DeokarS #fresh look #optimisation

A Fresh Look at Retiming Via Clock Skew Optimization (RBD, SSS), pp. 310–315.

DAC-1995-El-MalehMRM #on the #testing

On Test Set Preservation of Retimed Circuits (AHEM, TEM, JR, WM), pp. 176–182.

DAC-1995-KarkowskiO

Retiming Synchronous Circuitry with Imprecise Delays (IK, RHJMO), pp. 322–326.

DAC-1995-LalgudiP #modelling #named #performance

DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling (KNL, MCP), pp. 304–309.

DAC-1995-SinghalPRB

The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.

DAC-1994-ChakradharD

Resynthesis and Retiming for Optimum Partial Scan (STC, SD), pp. 87–93.

DAC-1993-IqbalPDP #algebra #using

Critical Path Minimization Using Retiming and Algebraic Speed-Up (ZI, MP, SD, ACP), pp. 573–577.

DAC-1993-KagarisT

Partial Scan with Retiming (DK, ST), pp. 249–254.