Proceedings of the 12th International Symposium on High-Performance Computer Architecture
HPCA, 2006.

@proceedings{HPCA-2006,
	address       = "Austin, Texas, USA",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2006/9368/00/index.html",
	isbn          = "0-7803-9368-6",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the 12th International Symposium on High-Performance Computer Architecture}",
	year          = 2006,
}

Contents (31 items)

8 ×#performance
6 ×#memory management
5 ×#named
4 ×#parallel
3 ×#architecture
3 ×#concurrent
3 ×#industrial
2 ×#design
2 ×#detection
2 ×#evolution

HPCA-2006-Shaw #architecture #biology

New architectures for a new biology (DES), p. 4.

HPCA-2006-ConstantinidesPBZBMAO #architecture #named

BulletProof: a defect-tolerant CMP switch architecture (KC, SP, JAB, BZ, VB, SAM, TMA, MO), pp. 5–16.

HPCA-2006-LiLBHS #constraints #design #physics

CMP design space exploration subject to physical constraints (YL, BCL, DMB, ZH, KS), pp. 17–28.

HPCA-2006-PenryFHWSAC #parallel #simulation

Exploiting parallelism and structure to accelerate the simulation of chip multi-processors (DAP, DF, DH, RW, GS, DIA, DC), pp. 29–40.

HPCA-2006-HuKLS #approach #implementation #performance

An approach for implementing efficient superscalar CISC processors (SH, IK, MHL, JES), pp. 41–52.

HPCA-2006-PericasCGJV

A decoupled KILO-instruction processor (MP, AC, RG, DAJ, MV), pp. 53–64.

HPCA-2006-SubramaniamL #dependence #memory management #predict #scalability #scheduling

Store vectors for scalable memory dependence prediction and scheduling (SS, GHL), pp. 65–76.

HPCA-2006-LiM #adaptation #parallel

Dynamic power-performance adaptation of parallel computation on chip multiprocessors (JL, JFM), pp. 77–87.

HPCA-2006-JaleelMJ #case study #data mining #mining #parallel #performance

Last level cache (LLC) performance of data mining workloads on a CMP — a case study of parallel bioinformatics workloads (AJ, MM, BLJ), pp. 88–98.

HPCA-2006-JosephVT #analysis #linear #modelling #performance #using

Construction and use of linear regression models for processor performance analysis (PJJ, KV, MJT), pp. 99–108.

HPCA-2006-Stenstrom #multi

Chip-multiprocessing and beyond (PS), p. 109.

HPCA-2006-RileyZ #predict #probability

Probabilistic counter updates for predictor hysteresis and stratification (NR, CBZ), pp. 110–120.

HPCA-2006-IsciM

Phase characterization for power: evaluating control-flow-based and event-counter-based techniques (CI, MM), pp. 121–132.

HPCA-2006-PandeyJZB #energy #memory management

DMA-aware memory energy management (VP, WJ, YZ, RB), pp. 133–144.

HPCA-2006-PujaraA #performance

Increasing the cache efficiency by eliminating noise (PP, AA), pp. 145–154.

HPCA-2006-VenkatesanHR #agile

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM (RKV, SH, ER), pp. 155–165.

HPCA-2006-ManovitH #consistency #memory management #verification

Completely verifying memory consistency of test program executions (CM, SH), pp. 166–175.

HPCA-2006-KimGS #comprehension #interactive

Understanding the performance-temperature interactions in disk I/O of server workloads (YK, SG, AS), pp. 176–186.

HPCA-2006-YuSHACGMPERTLG #performance

High performance file I/O for the Blue Gene/L supercomputer (HY, RKS, CH, GA, JGC, MG, JEM, JJP, TE, RBR, RT, RL, WDG), pp. 187–196.

HPCA-2006-NakanoMGT #named #performance

ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers (JN, PM, KG, JT), pp. 200–211.

HPCA-2006-Emma #capacity #evolution #industrial

Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth (PGE), p. 201.

HPCA-2006-Recio #evolution #industrial #network

Industrial Perspectives: System IO Network Evolution — Closing Requirement Gaps (RR), p. 201.

HPCA-2006-Yavatkar #challenge #design #framework #industrial #platform

Industrial Perspectives: Platform Design Challenges with Many cores (RY), p. 201.

HPCA-2006-KumarA #concurrent #detection #fault #performance

Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors (SK, AA), pp. 212–221.

HPCA-2006-ShiFGLZY #architecture #in memory #memory management #named #security

InfoShield: a security architecture for protecting information usage in memory (WS, JBF, GG, HHSL, YZ, JY), pp. 222–231.

HPCA-2006-Prvulovic #concurrent #detection #effectiveness #named

CORD: cost-effective (and nearly overhead-free) order-recording and data race detection (MP), pp. 232–243.

HPCA-2006-HuangGH #ambiguity #memory management

Software-hardware cooperative memory disambiguation (RH, AG, MCH), pp. 244–253.

HPCA-2006-MooreBMHW #memory management #named #transaction

LogTM: log-based transactional memory (KEM, JB, MJM, MDH, DAW), pp. 254–265.

HPCA-2006-ChungCMMCKO #behaviour #parallel #source code #thread #transaction

The common case transactional behavior of multithreaded programs (JC, HC, CCM, AM, BDC, CK, KO), pp. 266–277.

HPCA-2006-GontmakherMSS #concurrent #thread

Speculative synchronization and thread management for fine granularity threads (AG, AM, AS, GS), pp. 278–287.

HPCA-2006-SharkeyP #performance #smt

Efficient instruction schedulers for SMT processors (JJS, DVP), pp. 288–298.