Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
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Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce Jacob
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
HPCA, 2013.

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@inproceedings{HPCA-2013-ChangRLJ,
	author        = "Mu-Tien Chang and Paul Rosenfeld and Shih-Lien Lu and Bruce Jacob",
	booktitle     = "{Proceedings of the 19th International Symposium on High-Performance Computer Architecture}",
	doi           = "10.1109/HPCA.2013.6522314",
	isbn          = "978-1-4673-5585-8",
	pages         = "143--154",
	publisher     = "{IEEE Computer Society}",
	title         = "{Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM}",
	year          = 2013,
}

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