Stem stt$ (all stems)

30 papers:

DAC-2015-LiCSHLWY #hybrid #power management

A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.

DAC-2015-WangJZWY #energy #performance

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM (RW, LJ, YZ, LW, JY), p. 6.

DATE-2015-KomalanTPFC

System level exploration of a STT-MRAM based level 1 data-cache (MPK, CT, JIGP, FTF, FC), pp. 1311–1316.

DATE-2015-PajouhiFR #architecture #co-evolution #design #reliability

Device/circuit/architecture co-design of reliable STT-MRAM (ZP, XF, KR), pp. 1437–1442.

DATE-2015-VatajeluNIP

STT MRAM-Based PUFs (EIV, GDN, MI, PP), pp. 872–875.

DATE-2015-VatajeluRIRPF #estimation #metric #robust

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.

DAC-2014-EkenZWJLC #self

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability (EE, YZ, WW, RVJ, HL, YC), p. 6.

DAC-2014-SamavatianAAS #architecture #performance

An Efficient STT-RAM Last Level Cache Architecture for GPUs (MHS, HA, MA, HSA), p. 6.

DAC-2014-WenZMC #design #memory management #strict

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System (WW, YZ, MM, YC), p. 6.

DATE-2014-AshammagariMH #configuration management #design #functional #performance #power management

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design (ARA, HM, HH), pp. 1–6.

DATE-2014-BelKKS #fault #multi

Improving STT-MRAM density through multibit error correction (BDB, JK, CHK, SSS), pp. 1–6.

DATE-2014-BishnoiEOT #power management #symmetry #termination

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM (RB, ME, FO, MBT), pp. 1–6.

HPCA-2014-AhnYC #architecture #named #predict

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture (JA, SY, KC), pp. 25–36.

HPCA-2014-WangJXSX #adaptation #hybrid #migration #policy

Adaptive placement and migration policy for an STT-RAM-based hybrid cache (ZW, DAJ, CX, GS, YX), pp. 13–24.

DATE-2013-BiWL #design

STT-RAM designs supporting dual-port accesses (XB, MAW, HL), pp. 853–858.

DATE-2013-LiSLXCX #adaptation

Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.

DATE-2013-WangDX #named #policy

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches (JW, XD, YX), pp. 847–852.

HPCA-2013-ChangRLJ #comparison #energy #scalability

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (MTC, PR, SLL, BJ), pp. 143–154.

DAC-2012-JiangZZY #embedded #multi #performance #scalability

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors (LJ, BZ, YZ, JY), pp. 907–912.

DAC-2012-JogMXXNID #architecture #performance

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.

DAC-2012-MorrisBZP #logic #named #using

mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices (DM, DB, JG(Z, LTP), pp. 486–491.

DAC-2012-ParkGMRR #architecture #design #energy #performance #using

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture (SPP, SKG, NNM, AR, KR), pp. 492–497.

DAC-2012-WenZCWX #analysis #named #performance #reliability #scalability #statistics

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method (WW, YZ, YC, YW, YX), pp. 1191–1196.

DATE-2012-GuptaPMR #optimisation

Layout-aware optimization of stt mrams (SKG, SPP, NNM, KR), pp. 1455–1458.

DATE-2012-ZhangWLJC #design #symmetry

Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.

LCTES-2012-LiZXH #embedded #hybrid

Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache (QL, MZ, CJX, YH), pp. 109–118.

HPCA-2011-SmullenMNGS #energy #performance

Relaxing non-volatility for fast and energy-efficient STT-RAM caches (CWSI, VM, AN, SG, MRS), pp. 50–61.

DATE-2010-ChenLWZXZ #memory management #random #self

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (YC, HL, XW, WZ, WX, TZ), pp. 148–153.

DAC-2009-XuCWZ

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing (WX, YC, XW, TZ), pp. 87–90.

DAC-2008-LiASR #array #design #memory management #modelling #probability #random #statistics

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement (JL, CA, SSS, KR), pp. 278–283.