BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
S.Parameswaran M.S.Haque J.Peddersen A.Ignjatovic H.Javaid J.Henkel
Talks about:
cach (4) replac (3) polici (3) simul (3) processor (2) instruct (2) approach (2) rapid (2) embed (2) clock (2)

Person: Andhi Janapsatya

DBLP DBLP: Janapsatya:Andhi

Contributed to:

DAC 20102010
DATE 20102010
DATE 20072007

Wrote 5 papers:

DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
DATE-2010-JanapsatyaIPP #adaptation #algorithm #policy
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (AJ, AI, JP, SP), pp. 920–925.
DATE-2010-JavaidJHP #agile #estimation #pipes and filters #runtime
Rapid runtime estimation methods for pipelined MPSoCs (HJ, AJ, MSH, SP), pp. 363–368.
DATE-2007-JanapsatyaIPH #agile #simulation
Instruction trace compression for rapid instruction cache simulation (AJ, AI, SP, JH), pp. 803–808.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.