Travelled to:1 × France
1 × Germany
Collaborated with:E.J.Peralías A.Rueda N.M.Madrid J.L.Huertas P.Ruiz-de-Clavijo J.Juan-Chico M.J.Bellido M.Valencia
Talks about:design (2) model (2) methodolog (1) accuraci (1) pipelin (1) convert (1) signal (1) inerti (1) haloti (1) degrad (1)
Person: Antonio J. Acosta
DBLP: Acosta:Antonio_J=
Contributed to:
20012000Wrote 3 papers:
- DATE-2001-MadridPAR #design #modelling #reuse
- Analog/mixed-signal IP modeling for design reuse (NMM, EJP, AJA, AR), pp. 766–767.
- DATE-2001-Ruiz-de-ClavijoJBAV #logic #named
- HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model (PRdC, JJC, MJB, AJA, MV), pp. 467–471.
- DATE-2000-PeraliasARH #design #pipes and filters #verification
- A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.