Travelled to:1 × Germany
1 × USA
4 × France
Collaborated with:A.Rueda A.J.Ginés A.J.Acosta N.M.Madrid J.L.Huertas R.Seepold S.Mir T.Olbrich J.L.Huertas J.A.Prieto I.A.Grout A.M.D.Richardson
Talks about:design (4) methodolog (2) pipelin (2) switch (2) signal (2) analog (2) model (2) fault (2) reus (2) base (2)
Person: Eduardo J. Peralías
DBLP: Peral=iacute=as:Eduardo_J=
Contributed to:
20042002200120001998
1997Wrote 6 papers:
- DATE-v1-2004-GinesPR #fault #pipes and filters
- Digital Background Gain Error Correction in Pipeline ADCs (AJG, EJP, AR), pp. 82–87.
- DATE-2002-GinesPRSM #behaviour #design #modelling #parametricity #reuse
- A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects (AJG, EJP, AR, RS, NMM), pp. 310–314.
- DATE-2001-MadridPAR #design #modelling #reuse
- Analog/mixed-signal IP modeling for design reuse (NMM, EJP, AJA, AR), pp. 766–767.
- DATE-2000-PeraliasARH #design #pipes and filters #verification
- A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.
- DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
- DAC-1997-MirROPH #automation #evaluation #fault #named #simulation
- SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.