Travelled to:
5 × USA
Collaborated with:
∅ S.A.Mahlke W.W.Hwu M.S.Schlansker C.D.Glaeser E.M.Greenawalt N.J.Warter M.Lee P.P.Tirumalai W.Y.Chen
Talks about:
architectur (2) interconnect (1) superscalar (1) philosophi (1) processor (1) sentinel (1) multilay (1) horizont (1) support (1) softwar (1)
Person: B. Ramakrishna Rau
DBLP: Rau:B=_Ramakrishna
Contributed to:
Wrote 5 papers:
- PLDI-1993-WarterMHR
- Reverse If-Conversion (NJW, SAM, WmWH, BRR), pp. 290–299.
- ASPLOS-1992-MahlkeCHRS #scheduling
- Sentinel Scheduling for VLIW and Superscalar Processors (SAM, WYC, WmWH, BRR, MSS), pp. 238–247.
- PLDI-1992-RauLTS #pipes and filters
- Register Allocation for Software Pipelined Loops (BRR, ML, PPT, MSS), pp. 283–299.
- ASPLOS-1982-RauGG #architecture #generative #performance
- Architectural Support for the Efficient Generation of Code for Horizontal Architectures (BRR, CDG, EMG), pp. 96–99.
- DAC-1976-Rau #multi
- A new philosophy for interconnection on multilayer boards (BRR), pp. 225–231.