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Travelled to:
1 × Germany
1 × USA
Collaborated with:
E.Brockmeyer I.Issenin N.Dutt M.Dasygenis F.Catthoor D.Soudris A.Thanailakis
Talks about:
memori (3) multiprocessor (1) bottleneck (1) hierarchi (1) techniqu (1) prefetch (1) hierarch (1) perform (1) overcom (1) analysi (1)

Person: Bart Durinck

DBLP DBLP: Durinck:Bart

Contributed to:

DAC 20062006
DATE 20052005

Wrote 2 papers:

DAC-2006-IsseninBDD #analysis #memory management #multi #reuse
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (II, EB, BD, ND), pp. 49–52.
DATE-2005-DasygenisBDCST #energy #memory management #performance
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck (MD, EB, BD, FC, DS, AT), pp. 946–947.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.