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Travelled to:
3 × Germany
5 × France
8 × USA
Collaborated with:
S.Sarma A.BanaiyanMofrad I.Issenin S.Gupta A.Nicolau R.Gupta A.Nicolau N.Venkatasubramanian L.A.D.Bathen A.Shrivastava E.Brockmeyer P.Mishra P.Gupta L.Pozzi M.Gottscho H.Tajik H.Homayoun G.Girão Y.Paek Q.Zhu A.Gordon-Ross F.Vahid G.Ansaloni K.Tanimura S.Banerjee E.Bozorgzadeh J.Noguera B.Durinck M.Miranda M.Kim M.Stehr C.L.Talcott A.Kejariwal N.Bansal M.Shoushtari D.Cho S.Pasricha S.Ko S.Park E.Earlie P.Biswas V.Choudhary K.Atasu P.Ienne A.Khajeh A.Gupta F.J.Kurdahi A.M.Eltawil K.S.Khouri M.S.Abadir J.Henkel L.Bauer S.R.Nassif M.Shafique M.B.Tahoori N.Wehn H.Yagi W.Roesner T.Kogel E.Haritan H.Tangi M.McNamara G.Smith G.Mancini
Talks about:
memori (9) awar (5) explor (4) data (4) chip (4) architectur (3) reconfigur (3) processor (3) distribut (3) network (3)

Person: Nikil Dutt

DBLP DBLP: Dutt:Nikil

Contributed to:

DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20112011
DATE 20092009
DAC 20082008
DATE 20082008
LCTES 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20042004
DATE v1 20042004

Wrote 25 papers:

DAC-2014-DuttGNBGS #memory management #multi
Multi-Layer Memory Resiliency (ND, PG, AN, AB, MG, MS), p. 6.
DAC-2014-GottschoBDNG #capacity #energy #fault tolerance #scalability
Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches (MG, AB, ND, AN, PG), p. 6.
DAC-2014-SarmaVD #distributed #middleware #mobile #perspective
Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective (SS, NV, ND), p. 6.
DATE-2014-SarmaD #estimation #network #runtime
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking (SS, ND), pp. 1–6.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap
Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DAC-2013-TajikHD #3d #architecture #manycore #named #process
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture (HT, HH, ND), p. 8.
DATE-2013-BanaiyanMofradDG #analysis #distributed #fault tolerance #modelling
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip (AB, ND, GG), pp. 1605–1608.
DAC-2012-BathenD #distributed #hybrid #named
HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories (LADB, ND), pp. 447–452.
DATE-2011-AnsaloniPTD #array #configuration management #scheduling
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays (GA, LP, KT, ND), pp. 1513–1516.
DATE-2009-KhajehGDKEKA #design #memory management #named #reliability
TRAM: A tool for Temperature and Reliability Aware Memory Design (AK, AG, ND, FJK, AME, KSK, MSA), pp. 340–345.
DAC-2008-YagiRKHTMSDM #question
ESL hand-off: fact or EDA fiction? (HY, WR, TK, EH, HT, MM, GS, ND, GM), pp. 310–312.
DATE-2008-Dutt #design
Memory-aware NoC Exploration and Design (ND), pp. 1128–1129.
DATE-2008-KimSTDV #adaptation #constraints #online #refinement
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation (MK, MOS, CLT, ND, NV), pp. 646–651.
LCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation
Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
DAC-2007-BanerjeeBDN #architecture #configuration management #resource management #scheduling
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures (SB, EB, ND, JN), pp. 771–776.
DATE-2007-ZhuSD #functional #interactive #pipes and filters #validation
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines (QZ, AS, ND), pp. 1164–1169.
DAC-2006-IsseninBDD #analysis #memory management #multi #reuse
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (II, EB, BD, ND), pp. 49–52.
DATE-2006-ParkESNDP #automation #embedded #generative #performance
Automatic generation of operation tables for fast exploration of bypasses in embedded processors (SP, EE, AS, AN, ND, YP), pp. 1197–1202.
DAC-2004-BiswasCAPID #memory management #set
Introduction of local memory elements in instruction set extensions (PB, VC, KA, LP, PI, ND), pp. 729–734.
DAC-2004-KejariwalGNDG #algorithm #clustering #energy #mobile
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices (AK, SG, AN, ND, RG), pp. 556–561.
DATE-v1-2004-BansalGDNG #architecture #configuration management #network
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (NB, SG, ND, AN, RG), pp. 474–479.
DATE-v1-2004-Gordon-RossVD #automation #embedded
Automatic Tuning of Two-Level Caches to Embedded Applications (AGR, FV, ND), pp. 208–213.
DATE-v1-2004-GuptaDGN #control flow #design #synthesis
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (SG, ND, RG, AN), pp. 114–121.
DATE-v1-2004-IsseninBMD #analysis #memory management #reuse
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies (II, EB, MM, ND), pp. 202–207.
DATE-v1-2004-MishraD #functional #generative #graph #pipes and filters
Graph-Based Functional Test Program Generation for Pipelined Processors (PM, ND), pp. 182–187.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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